C1851BCU 데이터 시트보기 (PDF) - NEC => Renesas Technology
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C1851BCU Datasheet PDF : 60 Pages
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µPC1851B
2.2 SAP Demodulation Block
(1) SAP BPF
Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH. The filter response is
adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(2) Noise BPF
The µPC1851B monitors signals picked up by the noise BPF (fO =. . 180 kHz), and distinguishes noise from
signals. By this method, the µPC1851B prevents faulty SAP detection in a weak electric field. The filter response is
adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(3) Noise Detector
Performs full-wave rectification of noise from noise BPF, changes it to the DC voltage, and inputs it to the
comparator. When the noise level exceeds the reference level, the Noise detection bit (Read register, bit D4) turns
“1”.
The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor
connected to the NDT pin.
(4) SAP Detector
Detects the signal from the SAP BPF and smoothes it through the SDT pin and inputs it to the comparator. When
it detects the SAP signal, the SAP broadcast (Broadcast status) (Read register, bit D5) turns “1”.
(5) SAP Demodulator
The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit).
The SAP VCO oscillates at 10 fH, and performs phase comparison between the signal divided by 2 of the SAP
VCO frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the
SAP VCO SETTING bit (Write register, subaddress 05H, bits D0 to D5).
(6) SAP LPF
Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order LPF and fH trap filter. The
filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
Data Sheet S13417EJ2V0DS00
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