MT48H16M16LFF-8 데이터 시트보기 (PDF) - Micron Technology
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MT48H16M16LFF-8 Datasheet PDF : 58 Pages
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WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out ap-
pearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock
prior to the READ to bank m (Figure 26).
ADVANCE
256Mb: x16
MOBILE SDRAM
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The
PRECHARGE to bank n will begin after tWR is met,
where tWR begins when the WRITE to bank m is
registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to
bank m (Figure 27).
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
READ - AP
NOP
BANK m
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
READ with Burst of 4
NOP
tRP - BANK m
ADDRESS
DQ
NOTE: 1. DQM is LOW.
BANK n,
COL a
DIN
a
DIN
a+1
BANK m,
COL d
CAS Latency = 3 (BANK m)
DOUT
d
DOUT
d+1
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
NOP
BANK n
Internal
States
BANK m
Page Active
WRITE with Burst of 4
Page Active
WRITE - AP
NOP
NOP
NOP
BANK m
Interrupt Burst, Write-Back
tWR - BANK n
Precharge
tRP - BANK n
t WR - BANK m
WRITE with Burst of 4
Write-Back
ADDRESS
DQ
NOTE: 1. DQM is LOW.
BANK n,
COL a
DIN
a
DIN
a+1
DIN
a+2
BANK m,
COL d
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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