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ESD3V3U4ULC(2010) 데이터 시트보기 (PDF) - Infineon Technologies

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ESD3V3U4ULC
(Rev.:2010)
Infineon
Infineon Technologies Infineon
ESD3V3U4ULC Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
ESD3V3U4ULC
4
Application Information
Application Information
To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory.
To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low
device capacitance. The Infineon ESD3V3U4ULC in “array” configuration, combined with a clear and straight
forward “full through” layout fulfills these requirements in the best way.
SuperSpeed
Data IN
TX+
+
-
TX-
USB3.0: SS-Hub
e.g. PC
SuperSpeed
Data OUT
+ RX+
-
RX-
TVS ESD diodes
TX+
TX+
TX-
TX-
mated
connector
USB3.0 cable
SS transmission
channel
mated
connector
RX+
RX+
RX-
RX-
TVS ESD diodes
Figure 9 USB3.0 structure with ESD protection devices [3]
RX+
+
RX- -
SuperSpeed
Data OUT
USB3.0: SS-Device
e.g. storage
TX+
+
TX-
-
SuperSpeed
Data IN
Preliminary Data Sheet
13
Revision 0.9, 2010-10-14

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