HT45FM03B(2009) 데이터 시트보기 (PDF) - Holtek Semiconductor
부품명
상세내역
제조사
HT45FM03B Datasheet PDF : 83 Pages
| |||
HT45FM03B
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Interrupt Control Register - INTC0, INTC1, MFIC
These 8-bit registers, known as INTC0, INTC1 and
MFIC register, control the operation of both external and
internal interrupts. By setting various bits within this reg-
ister using standard bit manipulation instructions, the
enable/disable function of each interrupt can be inde-
pendently controlled. A master interrupt bit within this
register, the EMI bit, acts like a global enable/disable
and is used to set all of the interrupt enable bits on or off.
This bit is cleared when an interrupt routine is entered to
disable further interrupt and is set by executing the
²RETI² instruction.
Timer/Event Counter Registers
The device contains an 8-bit Timer/Event Counter and a
16-bit Timer/Event Counter. For the 8-bit Timer/Event
Counter an associated register known as TMR0 is the
location where the timer's 8-bit value is located. An as-
sociated control register, known as TMR0C, contains
the setup information for this timer. For the 16-bit
Timer/Event Counter two associated register known as
TMR1L and TRM1H are the locations where the timer's
16-bit values are located. An associated control register,
known as TMR1C, contains the setup information for
this timer.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC and PD. These
labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. with each I/O port there is an
associated control register labeled PAC, PBC, PCC and
PDC, also mapped to specific addresses with the Data
Memory. The control register specifies which pins of that
port are set as inputs and which are set as outputs. To
setup a pin as an input, the corresponding bit of the con-
trol register must be set high, for an output it must be set
low. During program initialization, it is important to first
setup the control registers to specify which pins are out-
puts and which are inputs before reading data from or
writing data to the I/O ports. One flexible feature of these
registers is the ability to directly program single bits us-
ing the ²SET [m].i² and ²CLR [m].i² instructions. The
ability to change I/O pins from output to input and vice
versa by manipulating specific bits of the I/O control reg-
isters during normal program operation is a useful fea-
ture of these devices.
Pulse Width Modulator Registers - PWM0H,
PWM0L, PWM1H, PWM1L, PWM2H, PWM2L,
PWMC0, PWMC1, PWMC2, PCPWMC, PCPWMD
The device contains a 3-channel 10-bit Pulse Width
Modulator function. Each PWM channel has its own
complementary pair of output and their own related reg-
ister pair, PWM0L/PWM0H, PWM1L/PWM1H, and
PWM2L/PWM2H as well as PWMC0, PWMC1,
PWMC2, PCPWMC and PCPWMD. The PWMxH and
PWMxL (x=0~2) register defines the duty cycle value for
the modulation cycle of the Pulse Width Modulator
PWM0 or PWM1 or PWM2.
A/D Converter Registers -
ADRL, ADRH, ADCR, ACSR
The device contains an 8-channel 12-bit A/D converter.
The correct operation of the A/D requires the use of two
data registers, a control register and a clock source reg-
ister. The two data registers, a high byte data register
known as ADRH, and a low byte data register known as
ADRL, are the register locations where the digital value
is placed after the completion of an analog to digital con-
version cycle. The channel selection and configuration
of the A/D converter is setup via the control register
ADCR while the A/D clock frequency is defined by the
clock source register, ACSR.
Analog Comparator Control Register - CMPC
This register is used to provide control over the internal
Analog Comparator function.
Miscellaneous Control Register - MISC
This register is used to provide control over the internal
Analog Comparator and PWM functions.
Operation Amplifier Control Register - OPAC
This register is used to provide control over the internal
Operation Amplifier function.
Rev. 1.00
18
December 16, 2009
Share Link: 