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LXT970AQC

Dual-Speed Fast Ethernet Transceiver

Intel 

LXT970A — Dual-Speed Fast Ethernet Transceiver

2.0

Functional Description

2.1

Introduction

The LXT970A, a new-generation version of the LXT970 10/100 PHY Fast Ethernet Transceiver

incorporates several functional enhancements for a more robust Ethernet solution. The LXT970A

supports optional MII driver strength capabilities and link-loss criteria selectable via the MDIO

register set.

The LXT970A can directly drive a twisted-pair cable for up to 100 meters. The LXT970A also

provides a pseudo-ECL interface for driving a 100BASE-FX fiber connection. On power-up, the

LXT970A uses auto-negotiation with parallel detection to automatically determine line operating

conditions. If the PHY device on the other side of the link supports auto-negotiation, the

LXT970A auto-negotiates using Fast Link Pulse (FLP) bursts. If the PHY partner does not support

auto-negotiation, the LXT970A automatically detects the presence of either link pulses (10 Mbps

PHY) or Idle symbols (100 Mbps PHY) and set its operating speed accordingly. When the line

speed selection is made via the parallel detection method, the duplex mode sets to half. The user

may later select full-duplex operation by subsequent writes to the appropriate MDIO register. Line

operation can also be set using the Hardware Control Interface.

The LXT970A interfaces to a 10/100 MAC through the MII interface. The LXT970A performs all

functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer

as defined in the IEEE 802.3 100BASE-X specification. It also performs all Physical Media

Dependent (PMD) sublayer functions for 100BASE-TX connections. The MII speed is

automatically set once line operating conditions have been determined.

See Figure 3 for a typical Network Interface Card (NIC). The LXT970A supports NIC, repeater,

and switch applications. It provides half- and full-duplex operation at 100 Mbps and 10 Mbps. The

LXT970A supports the 802.3 MDIO register set. Specific bits in the registers are referenced using

an “X.Y” notation, where X is the register address (0-6 or 16-20) and Y is the bit number (0:15).

Figure 3. Network Interface Card (NIC) Application

PC Bus (EISA,PCI)

MAC Controller

LXT970A

Magnetic

RJ-45

Connection

18

Datasheet

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