MAX16050ETI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX16050ETI

Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability

Maxim Integrated 

MAX16050/MAX16051

Voltage Monitors/Sequencer Circuits with

Reverse-Sequencing Capability

consumption. Use the following equation to estimate the

value of the resistors based on the amount of acceptable

error:

R1 = e A × V1TH

ISET

where eA is the fraction of the maximum acceptable

absolute resistive divider error attributable to the input

leakage current (use 0.01 for ±1%), V1TH is the power-

good threshold for the power supply being monitored,

and ISET is the worst-case SET_ input leakage current

(see the Electrical Characteristics table). Calculate R2 as

follows:

R2 = VTH × R1

V1TH − VTH

The eA error adds to any errors caused by the resistive

voltage divider.

Pullup Resistor Values

The exact value of the pullup resistors for the open-drain

outputs is not critical, but some consideration should be

made to ensure the proper logic levels when the device is

sinking current. For example, if VCC = 3.3V and the pullup

voltage is 5V, keep the sink current less than 3.2mA as

shown in the Electrical Characteristics table. As a result,

the pullup resistor should be greater than 1.6kΩ. For a

12V pullup, the resistor should be larger than 3.74kΩ.

Extra care must be taken when using CP_OUT as the

pullup voltage. If multiple pullup resistors are connected

to CP_OUT, any OUT_ pin that goes low will draw a

current from CP_OUT. If this current is too high, it can

drop the CP_OUT voltage enough to prevent other

enabled MOSFETs from turning on completely. See CP_

OUT VOLTAGE vs. CP_OUT CURRENT in the Typical

Operating Characteristics.

Daisy-Chaining the MAX16050/MAX16051

Multiple MAX16050/MAX16051 devices can be daisy-

chained to sequence and monitor a large number of voltages

Figure 7 shows an example of two daisy-chained devices.

When a fault occurs on any of the monitored inputs,

FAULT goes low, signaling a fast power-down. Connect

all FAULT pins of the MAX16050/MAX16051 together to

ensure that all power supplies are turned off during a fault.

In Figure 7, for proper turn-on, U1 RESET is connected

to U2 EN to ensure power-up sequencing for all voltage

rails. For turn off, SHDN is pulled low to initiate the power-

down sequence. When all of the supply voltages moni-

tored by U2 are off, the bus removal output (REM) goes

high, thereby allowing U1 to start sequencing down. REM

normally is at a logic-low state when all voltages are good.

Connect U2’s REM to U1’s EN_HOLD to force U1 to stay

on even if EN and SHDN are pulled low. This enable-and-

hold circuitry allows the system to power down correctly.

MOSFET Selection

The external pass MOSFET connects in series with the

sequenced power-supply source. Since the load current

and the MOSFET drain-to-source impedance (RDSON)

determine the voltage drop, the on-characteristics of the

MOSFET affect the load supply accuracy. For highest sup-

ply accuracy and lowest voltage drop, select a MOSFET

with an appropriate drain-to-source on-resistance with a

gate-to-source bias of 4.5V to 6.0V (see Table 2).

Layout and Bypassing

For better noise immunity, bypass VCC to GND with a

0.1μF capacitor installed as close to the device as pos-

sible. Bypass ABP to GND with a 1μF capacitor installed

as close to the device as possible. Connect the exposed

pad (EP) to the ground plane for improved heat dissipa-

tion. Do not use EP as the only ground connection for the

device.

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