MAX16024PTBT25T 데이터 시트보기 (PDF) - Maxim Integrated

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MAX16024PTBT25T

Battery-Backup Circuits with Regulated Output Voltage

Maxim Integrated 

Battery-Backup Circuits with

Regulated Output Voltage

Detailed Description

The Typical Applications Circuit shows a typical con-

nection using the MAX16024. OUT powers the SRAM. If

VCC is higher than the reset threshold (VTH), or if VCC is

lower than VTH but higher than VBATT, the regulator is

powered from VCC. If VCC < VTH, VCC < VBATT, and the

regulator is in dropout, the regulator is powered from

BATT (see the Functional Diagrams). OUT supplies up

to 100mA from VCC.

Backup-Battery Switchover

In a brownout or power failure, it may be necessary to

preserve the contents of the RAM. With a backup-bat-

tery installed at BATT, the MAX16023/MAX16024 auto-

matically switch the RAM to backup power when VCC

falls. The MAX16024 has a BATT ON output that goes

high when in battery-backup mode. Three conditions

must be met for these devices to switch to battery

backup mode:

1) VCC is lower than the reset threshold.

2) VCC is lower than VBATT.

3) The regulator is in dropout (except for the 1.2V out-

put version).

Chip-Enable Signal Gating (MAX16024)

The MAX16024 provides internal gating of CE signals to

prevent erroneous data from being written to CMOS

RAM in the event of a power failure or brownout. During

normal operation, the CE gate enables and passes all

CE transitions. When the reset output asserts, this path

becomes disabled, preventing erroneous data from cor-

rupting the CMOS RAM and CEOUT is pulled up to OUT

through an internal current source. The 1.5ns propaga-

tion delay from CEIN to CEOUT allows the devices to

be used with most µPs and high-speed DSPs.

During normal operation (reset not asserted), CEIN is

connected to CEOUT through a low on-resistance

transmission gate. If CEIN is high when a reset asserts,

CEOUT remains high regardless of any subsequent

transition on CEIN during the reset event.

If CEIN is low when reset asserts, CEOUT is held low for

12µs to allow completion of the read/write operation.

After the 12µs delay expires, CEOUT goes high and

stays high regardless of any subsequent transitions on

CEIN during the reset event. When CEOUT is discon-

nected from CEIN, CEOUT is actively pulled up to OUT.

The propagation delay through the chip-enable circuitry

depends on both the source impedance of the drive to

CEIN and the capacitive loading at CEOUT. Minimize

the capacitive load at CEOUT to minimize propagation

delay, and use a low-output-impedance driver.

VCC

RESET THRESHOLD VTH

CEIN

CEOUT

RESET-TO-CEOUT DELAY (12µs)

tRD

RESET

tRD

tRP

*

tRP

Figure 1. Reset and Chip-Enable Timing

* IF CEIN GOES HIGH BEFORE RESET ASSERTS,

CEOUT GOES HIGH WITHOUT DELAY AS

CEIN GOES HIGH.

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