MB90822 데이터 시트보기 (PDF) - Fujitsu
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MB90822 Datasheet PDF : 100 Pages
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MB90820 Series
■ BLOCK DIAGRAM
X0
Clock control
X1
circuit
Reset circuit
RST
(Watchdog timer)
Interrupt controller
P51/INT7
P16/INT6 to 6
P11/INT1
P45/SIN0
P44/SOT0
P43/SCK0
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P40/PPG1
P50/PPG2
P46/PWI1
P47/PWO1
8
DTP/External interrupt
UART
(ch0)
UART
(ch1)
16-bit PPG
(ch1)
16-bit PPG
(ch2)
PWC
(ch1)
P42/TO0
P41/TIN0
16-bit reload timer
(ch0)
P21/TO1
P20/TIN1
P22 to P27 6
16-bit reload timer
(ch1)
CMOS I/O port 1, 2, 4, 5, 7
RAM
ROM
ROM correction
ROM mirroring
CPU
F2MC-16LX core
Other pins
Vss × 2, Vcc × 2, MD0 to MD2, C
Timebase timer
Delayed interrupt generator
Multi-functional timer
16-bit PPG timer
(ch0)
16-bit input capture 4
(ch0 to ch3)
16-bit free-running
timer
16-bit output
compare
(ch0 to ch5)
Waveform
generator
PWC
(ch0)
CMOS I/O port 0, 1, 3, 7, 8
7
P30 to P36
P37/PPG0
4
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P75/FRCK/AN13
P82/RTO0 (U) *
P83/RTO1 (X) *
P84/RTO2 (V) *
P85/RTO3 (Y) *
P86/RTO4 (W) *
P87/RTO5 (Z) *
P10/INT0/DTTI
P17
P06/PWI0 *
P07/PWO0 *
6
P00 to P05 *
CMOS I/O port 6
A/D converter
16
(8/10-bit)
8-bit D/A converter
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVR
AVCC
AVSS
P70/DA0/AN8
P71/DA1/AN9
CMOS I/O port 7
Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used
as input pull-up resistors.
* : High current drive pin.
18
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