MB90822 데이터 시트보기 (PDF) - Fujitsu
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MB90822 Datasheet PDF : 100 Pages
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MB90820 Series
(Continued)
Address
0000C0H
0000C1H
0000C2H
0000C3H
0000C4H
0000C5H
0000C6H
0000C7H
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
0000D1H to
0000EFH
0000F0H to
0000FFH
001FF0H
001FF1H
001FF2H
001FF3H
001FF4H
001FF5H
Abbrevia-
tion
PWCSL0
PWCSH0
PWC0
DIV0
ADER0
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
DAT0
DAT1
DACR0
DACR1
ADER1
PADRL0
PADRM0
PADRH0
PADRL1
PADRM1
PADRH1
Register
Byte ac- Word
cess access
Resource name
Initial
value
PWC control status register R/W R/W
ch0
R, R/W R, R/W
00000000B
00000000B
PWC data buffer register ch0 ⎯
R/W
PWC timer (ch0)
XXXXXXXXB
XXXXXXXXB
Divide ratio control register
ch0
R/W
R/W
XXXXXX00B
A/D input enable register 0 R/W R/W
Port 6, A/D
11111111B
A/D control status register 0 R/W R/W
000XXXX0B
A/D control status register 1 W, R/W W, R/W
0000000XB
A/D data register 0
A/D data register 1
R
R
XXXXXXXXB
8/10-bit A/D converter
R
R
XXXXXXXXB
A/D setting register 0
R/W R/W
00000000B
A/D setting register 1
R/W R/W
00000000B
D/A data register 0
R/W R/W
XXXXXXXXB
D/A data register 1
D/A control register 0
R/W R/W
XXXXXXXXB
8-bit D/A converter
R/W R/W
XXXXXXX0B
D/A control register 1
R/W R/W
XXXXXXX0B
A/D input enable register 1 R/W R/W
Port 7, A/D
11111111B
Prohibited area
External area
Program address detection
register 0 (lower)
R/W
R/W
Program address detection
register 0 (middle)
R/W
R/W
Program address detection
register 0 (higher)
R/W
R/W
Program address detection
register 1 (lower)
R/W
R/W
Program address detection
register 1 (middle)
R/W
R/W
Program address detection
register 1 (higher)
R/W
R/W
Address match
detection
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
• Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R : Read-only
W : Write-only
• Explanation of initial values
0 : The bit is initialized to “0”.
1 : The bit is initialized to “1”.
X : The initial value of the bit is undefined.
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