SC220C6B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SC220C6B

XpressFlow Engine XpressFlow 2020 Ethernet Routing Switch Chipset

Zarlink Semiconductor Inc 

PRELIMINARY

XpressFlow-2020 Series –

Ethernet Switch Chipset

INFORMATION

SC220

XpressFlow Engine

2 FUNCTIONAL DESCRIPTION

2.1 CAM Interface

t Direct interface with MUSIC MU9C1480 1k x

64 bit Content Addressable Memory (CAM)

◊ Expandable to support 8k MAC Addresses

t Two access masters: HISC in XpressFlow

Engine, and Switch Manager CPU

t Master interface with CAM Interface logic via

two dedicated CAM Command Blocks

◊ One for HISC

CAM

CAM

Interface

Logic

Command

Block

Response

Data Block

From HISC

To HISC

Command

Block

Response

Data Block

From CPU

To CPU

◊ One for Switch Manager CPU

Block Diagram – CAM Interface

t Both HISC and Switch Manager CPU can ac-

cess the CAM by setting up their corresponding CAM Command Blocks, and read the return informa-

tion from their own Response Data Block

2.1.1 Pin Description

Symbol

C_D[15:0]

C_CE#

C_WE#

C_CM#

C_EC#

C_MF#

C_FF#

Type Name & Functions

TTL CAM Data Bus bit [15:0] – a 16-bit data bus for Data/Command in-

I/O-TS put/output.

CMOS CAM Chip Enable – Enables the CAM by registers the control signals

Output on its falling edge and release them on its rising edge. Also used for

locking and unlocking the cascaded daisy chain.

CMOS CAM Write Enable – allows to write data or command to CAM

Output

CMOS CAM Data/Command Select – defines data or command operations

Output

CMOS CAM Enable Comparison – latches and enables the MF and FF outputs

Output during a comparison cycle.

TTL CAM Match Flag – indicates a valid match during a comparison cycle.

Input

TTL CAM Full Flag – indicates there is no empty location in the CAM.

Input

© 1998 Vertex Networks, Inc.

11

1999

Rev. 4.5 – February

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