SC220C5P 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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SC220C5P Datasheet PDF : 34 Pages
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PRELIMINARY
XpressFlow-2020 Series –
Ethernet Switch Chipset
INFORMATION
SC220
XpressFlow Engine
I/O Offset
Register Description
Little Big Reg.
Endian Endian Size
Buffers & Stacks Management (Continue)
Switch Control Buffers
SCBBA Switch Control Buffer – Base Address
hC00 hC02 16-bit
SCBA Switch Control Buffer – Buffer Allocation
hC20 hC22 16-bit
SCBAG Switch Control Buffer – Buffer Aging Status
hC30 hC32 16-bit
SCBSA Switch Ctrl Buffer Stack – Base Address
hC80 hC82 16-bit
SCBSL Switch Ctrl Buffer Stack – Size Limit
hC90 hC92 16-bit
SCBST Switch Ctrl Buffer Stack – Buffer Low Threshold hCA0 hCA2 16-bit
SCBSS Switch Ctrl Buffer Stack – Allocation Status
MAC Control Tables
MCTA MAC Control Table – Table Allocation
hCB0 hCB2 16-bit
hB20 hB22 16-bit
MCTR MAC Control Table – Table Release
hB20 hB22 16-bit
MCTSA MAC Ctrl Table Stack – Base Address
hB80 hB82 16-bit
MCTSS MAC Ctrl Table Stack – Allocation Status
hBB0 hBB2 16-bit
Queue Management
QSBA Queue Structure – Base Address
hA00 hA02 16-bit
MFTA Multicast Frame Table – Base Address
hA10 hA12 16-bit
CINQ CPU Input Queue
hA88 hA88 32-bit
COTQ
CSQ0
CSQ1
CSQ2
CPU Output Queue
CPU Status Queue – 1st D-word
CPU Status Queue – 2nd D-word
CPU Status Queue – 3rd D-word
hA88
hA98
hAA8
hAB8
hA88
hA98
hAA8
hAB8
32-bit
32-bit
32-bit
32-bit
CAM Interface
CCWR CAM Command/Data Write Register
h908 h908 32-bit
CSRL CAM Status/Data Read Register Low
h928 h928 32-bit
CSRH CAM Status/Data Read Register High
h938 h938 32-bit
HISC Control
HPCR HISC Processor Control Register
h980 h982 16-bit
HMCL HISC Micro-Code Loading Port
h998 h998 32-bit
HPRC HISC Priority Control Register
h9B0 h9B2 16-bit
W/R
W/R
--/R
--/R
W/R
W/R
W/R
--/R
--/R
W/-
W/R
--/R
W/R
W/R
W/--
--/R
--/R
--/R
--/R
W/--
--/R
--/R
W/R
W/R
W/R
Note:
© 1998 Vertex Networks, Inc.
19
1999
Rev. 4.5 – February
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