SC220 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SC220

XpressFlow Engine XpressFlow 2020 Ethernet Routing Switch Chipset

Zarlink Semiconductor Inc 

PRELIMINARY

XpressFlow-2020 Series –

Ethernet Switch Chipset

2.4 XpressFlow Bus Interface

t Vertex Networks’ optimized XpressFlow Bus

architecture

t Provides 1G bps switching bandwidth

t Full multi bus master structure

t Allows XpressFlow Engine to communicate

with Access Controllers via a message pass-

ing protocol

◊ Command Messages for passing control

information between devices

INFORMATION

SC220

XpressFlow Engine

◊ Data Messages for forwarding an Ethernet

frame from receiving port to transmission

port

t Built-in intelligent bus load regulator for data

traffic balancing

t Provides centralized bus arbitration with two

level request priorities

◊ High priority for Data Messages

◊ Low priority for Command Messages

2.4.1 Pin Description

Symbol Type Name & Functions

S_D[31:0]

S_MSGEN#

S_EOF#

S_IRDY

S_TABT#

S_HPREQ#

S_REQ[8:1]#

S_GNT[8:1]#

S_OVLD#

S_CLK

CMOS Data Bus Bit [31:0] – a 32-bit synchronous data bus.

I/O-TS Note: During the system RESET period, Data Bit [31:28] are used as

Processor Interface Configuration bit [0:3]

CMOS Message Envelope – encompasses the entire period of a message

I/O-TS transfer. Targets use the leading edge of this signal to detect the be-

ginning of a message transfer, and to decode the message header for

the intended target(s).

CMOS End of Frame – only used by frame data transfer messages to identify

I/O-TS the end of frame condition. This signal is synchronous with the Rx

Frame Status word appended to the end of the message.

CMOS Initiator Ready – a normal true signal. When negated, it indicates the

I/O-TS initiator had asserted wait state(s) in between command words. Target

should use this signal as enable signal for latching the data from the

bus.

CMOS Target Abort – when asserted, the target had aborted the reception of

I/O-OD current message on the bus.

CMOS High Priority Request – indicates one or more Bus Requester is re-

I/O-OD questing for high priority message transfer.

CMOS Bus Request [8:1] – Bus Request signals from Access Controllers to

Input Bus Access Arbitrator in XpressFlow Engine

CMOS Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus Re-

Output questers

CMOS Bus Overload – when asserted all data forwarding bus bandwidth has

Output been allocated. Cannot support additional load for data forwarding traf-

fic

CMOS XpressFlow Bus Clock – 33MHz system clock

Input

© 1998 Vertex Networks, Inc.

20

1999

Rev. 4.5 – February

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