SPHE8281D 데이터 시트보기 (PDF) - Unspecified
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SPHE8281D Datasheet PDF : 35 Pages
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Preliminary
SPHE8281D/Dx
Symbol
M_DD[3]
VDD_O2
M_DD[2]
M_DD[1]
M_DD[0]
M_W E_B
M_CAS_B
M_RAS_B
VSS_O2/ VSS_K2
M_CS0_B/GPIO
M_BA0
M_DD[15]
M_DD[14]
M_DD[13]
VDD_K2
M_DD[12]
M_DD[11]
M_DD[10]
M_DD[9]
M_DD[8]
M_A[11]/ GPIO
VDD_O3
M_CLKO
VSS_O3/ VSS_K3
M_CKE/GPIO
M_A[9]
M_A[8]
M_A[7]
M_A[6]
M_A[5]
Pin No. I/O
91
IO
92
S
93
IO
94
IO
95
IO
96
IO
97
IO
98
IO
99
S
100
IO
101
IO
102
IO
103
IO
104
IO
105
S
106
IO
107
IO
108
IO
109
IO
110
IO
111
IO
112
S
113
O
114
S
115
IO
116
IO
117
IO
118
IO
119
I/O
120
I/O
Description
SDRAM data bus [3]
I/O power supply #2
SDRAM data bus [2]
SDRAM data bus [1]
SDRAM data bus [0]
SDRAM write enable / row precharge
SDRAM column address strobe (CASB)
SDRAM row address strobe (RASB)
Kernel logic / I/O power shared ground supply #2
SDRAM chip select 0, or GPIO[24]
Priority selection
sft_cfg0[0]=1’b1
Function
SDRAM chip select
sft_cfg8[9]=1’b1
(default)
DAC_DATA_D[2]
(other)
GPIO[24]
SDRAM bank select address [0]
SDRAM data bus [15]
SDRAM data bus [14]
SDRAM data bus [13]
Kernel logic power supply #2
SDRAM data bus [12]
SDRAM data bus [11]
SDRAM data bus [10]
SDRAM data bus [9]
SDRAM data bus [8]
SDRAM address bus [11] or GPIO[25]
Priority selection
sft_cfg1[4]=1’b1
Function
SDRAM address bus
sft_cfg8[9]=1’b1
M_A[11] (default)
DAC_DATA_C[2]
(other)
GPIO[25]
I/O power supply #3
SDRAM clock output
Kernel logic / I/O power shared ground supply #3
SDRAM clock enable, or GPIO[26]
Priority selection
sft_cfg0[1]=1’b1
Function
DRAM clock enable
sft_cfg8[9]=1’b1
(default)
DAC_DATA_C[1]
(other)
GPIO[26]
SDRAM address bus [9]
SDRAM address bus [8]
SDRAM address bus [7]
SDRAM address bus [6]
SDRAM address bus [5]
© Sunplus Confidential
15
Contents are subject to change without Notice
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MAY. 19, 2005
Preliminary Version: 0.1
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