STE2002DIE2 데이터 시트보기 (PDF) - STMicroelectronics
부품명
상세내역
제조사
STE2002DIE2 Datasheet PDF : 61 Pages
| |||
STE2002
Circuit description
Figure 3. Bias level generator
R
R
nR
R
R
VLCD
n+3
n + 4 ·VLCD
n+2
n + 4 ·VLCD
2
n + 4 ·VLCD
1
n + 4 ·VLCD
VSS D00IN1150
thus providing an 1/(n+4) ratio, with n calculated from:
= m–
For m = 81, n = 6 and an 1/10 ratio is set.
For m = 65, n =5 and an 1/9 ratio is set.
The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio
as shown below:
Table 2. Bias ratio programming
BS2
BS1
BS0
n
0
0
0
7
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
The following table Bias Level for m = 65 and m = 81 are provided:
Table 3.
Bias level
Symbol
V1
V2
V3
V4
V5
V6
m = 65 (1/9)
VLCD
8/9*VLCD
7/9*VLCD
2/9*V VLCD
1/9 *VLCD
VSS
m = 81 (1/10)
VLCD
9/10*VLCD
8/10*VLCD
2/10*VLCD
1/10*VLCD
VSS
9/61
Share Link: 