ZR36505 데이터 시트보기 (PDF) - Unspecified

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ZR36505

USBvision™ II Data Decoder

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ZORAN Corporation

USBvision II Data Decoder

ZR36505 Data Sheet

Product Description

Refer to Fig.1 for an internal Block Diagram of the ZR36505.

ZR36505 CHIP

from

ZR36504

Serial

Control

pins

from

Video

Decoder.

27MHz

48MHz

from

ZR36504

IIC

Serial Interface

VBI DATA

QUALIFIER

Control Registers

Status Registers

Prog.

I/O

Remote Control

IR Binary Sampler

(4KHz)

1KB

Buff

BULK

INTERFAC

E

General

purpose

I/O pins

(Remote

Control,

IRD,

etc.)

to

ZR36504

Bulk pins

(0-2Mbps)

Fig.1 ZR36505 Block Diagram

The IIC block uses the LRNACK mode of the ZR36504 serial control bus to provide

access to its internal registers. The address range for output registers and input registers is

0x00-0x07 each.

The internal Input and Output Registers are used by the Host (PC S/W via ZR36504) to

control the parameters of the ZR36505 blocks and to read their status. There are two

general I/O pins to be used by S/W for specific designs.

The VBI DATA QUALIFIER block can be programmed to restrict VBI data capture to

any specified range of lines within the video field. Also, a specific data type can be defined,

to filter out all other types of VBI data.

The 1KByte Buffer is used for capturing all VBI data from every coming video field (after

qualification), and sending it via the Bulk Interface. This is done for one field at a time, and

Write/Read cannot be done simultaneously.

The BULK INTERFACE block is designed to match the ZR36504 specification. It can

coexist with an audio Codec source to share the same clock and data pins of the NT1004.

Finally, The ZR36505 uses 2 clock sources: 27MHz for VBI data, and 48MHz (from

NT1004) for the other blocks. The ZR36505 does not require a crystal of its own.

November-99

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