ALC5640CG 데이터 시트보기 (PDF) - Realtek Semiconductor

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ALC5640CG

Multi-Channel Audio Hub/CODEC and SounzReal Digital Sound Effect for Mobile Devices

Realtek Semiconductor 

ALC5640-VB

Datasheet

7.4.2. I2C and Two I2S/PCM Interface

The ALC5640 supports I2C for the digital control interface, and has two I2S/PCM for digital data

interface. These two I2S/PCM audio digital interfaces are used to send data to 4 DACs or to receive data

from a stereo ADC. These two I2S/PCM audio digital interfaces can be configured to Master mode or

Slave mode.

Master Mode

Under master mode, BCLK and LRCK are configured as output. If I2S SYSCLK is selected from MCLK

source, sel_sysclk1 (MX-80[15:14]) should set as 00’b. If selected from PLL output, sel_sysclk1 should

set as 01’b. PLL’s source is suggested to provide frequency from 2.048MHz to 40MHz. The driver

should set each divider (MX-73 and MX-89) to arrange the clock distribution. Refer to Figure5. Audio

Clock Tree, for details.

Register Settings

MX-73[15]=0’b

MX-73[15]=1’b

MX-73[15]=0’b

MX-73[15]=1’b

Table 12. The relative of SYSCLK/BCLK/LRCK

MCLK

BCLK

256*FS=12.288MHz

32*FS=1.536MHz

256*FS=12.288MHz

64*FS=3.072MHz

256*FS=11.2896MHz

32*FS=1.4112MHz

256*FS=11.2896MHz

64*FS=2.8224MHz

LRCK

FS=48KHz

FS=48KHz

FS=44.1KHz

FS=44.1KHz

Example for master mode:

Target format:

Sample Rate: 48 KHz

Channel Length: 32 bits

LRCK=48KHz

BCLK=3.072MHz (64 * 48KHz)

MCLK clock request:

MCLK=12.288MHz (256 * 48 KHz)

Register settings:

Set MX-FA[0] to “1”

Set MX-61[15] to “1”

Set MX-70[15] to “0”

Set MX-73[15] to “1”

Set MX-73[14:12] to “000”

// For MCLK input clock getting control

// Enable I2S-1

// Enable Master mode

// Select 64*FS for BCLK in master mode

// Select I2S-1 pre-divider

Multi-Channel Audio Hub/CODEC and SounzRealTM

18

Digital Sound Effect for Mobile Devices

Rev. 0.91

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