ALC5616 데이터 시트보기 (PDF) - Realtek Semiconductor
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ALC5616 Datasheet PDF : 104 Pages
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ALC5616
Datasheet
7.4.1. Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK, BCLK1 by setting register.
The S/W driver can set up the PLL to output a frequency to match the requirement of system clock.
The PLL transmit formula as below:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
MCLK
13
3.6864
2.048
4.096
12
15.36
16
19.2
19.68
24
Table 9.
N
66
78
94
70
80
81
78
80
78
39
Clock Setting Table for 48K (Unit: MHz)
M
FVCO
K
7
98.222
2
1
98.304
2
0
98.304
2
1
98.304
2
8
98.4
2
11
98.068
2
11
98.462
2
14
98.4
2
14
98.4
2
8
98.4
2
FOUT
24.555
24.576
24.576
24.576
24.6
24.517
24.615
24.6
24.6
24.6
MCLK
13
3.6864
2.048
4.096
12
15.36
16
19.2
19.68
24
Table 10.
N
68
72
86
64
66
63
66
64
67
62
Clock Setting Table for 44.1K (Unit: MHz)
M
FVCO
K
8
91
2
1
90.931
2
0
90.112
2
1
90.112
2
7
90.667
2
9
90.764
2
10
90.667
2
12
90.514
2
13
90.528
2
15
90.352
2
FOUT
22.75
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
22.588
I2S Audio CODEC for Mobile Devices
14
Rev. 0.1
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