MFRC52201HN1/TRAYB 데이터 시트보기 (PDF) - NXP Semiconductors.

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MFRC52201HN1/TRAYB

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

8.1.4.8 High-speed mode

In High-speed mode (HS mode), the device can transfer information at data rates of up to

3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode

(F/S mode) for bidirectional communication in a mixed-speed bus system.

8.1.4.9 High-speed transfer

To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to

I2C-bus operation.

• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger

on the SDA and SCL inputs and different timing constants when compared to

F/S mode

• The output buffers of the device in HS mode incorporate slope control of the falling

edges of the SDA and SCL signals with different fall times compared to F/S mode

8.1.4.10 Serial data transfer format in HS mode

The HS mode serial data transfer format meets the Standard mode I2C-bus specification.

HS mode can only start after all of the following conditions (all of which are in F/S mode):

1. START condition (S)

2. 8-bit master code (00001XXXb)

3. Not-acknowledge bit (A)

When HS mode starts, the active master sends a repeated START condition (Sr) followed

by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from

the selected MFRC522.

Data transfer continues in HS mode after the next repeated START (Sr), only switching

back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,

a master links a number of HS mode transfers, separated by repeated START conditions

(Sr).

F/S mode

HS mode (current-source for SCL HIGH enabled)

F/S mode

S MASTER CODE A Sr SLAVE ADDRESS R/W A

DATA

A/A P

(n-bytes + A)

HS mode continues

Fig 18. I2C-bus HS mode protocol switch

Sr SLAVE ADDRESS

001aak749

MFRC522

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 27 April 2016

112139

© NXP Semiconductors N.V. 2016. All rights reserved.

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