2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
ADDRESS A17-0
BES#
BEF#
OE#
WE#
DQ6
TOEH
TBE
TOE
FIGURE 8: FLASH TOGGLE BIT TIMING DIAGRAM
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
392 ILL F07.0
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS A17-0
5555 2AAA
5555
5555
2AAA
SAX
BES#
BEF#
OE#
WE#
TWP
DQ7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchangeable as long as minimum timings are met. (See Table 12)
SAX = Sector Address
FIGURE 9: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
14
392 ILL F08.1
S71137-03-000 10/01 392