AB28F200BR-B80 데이터 시트보기 (PDF) - Intel

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AB28F200BR-B80

2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

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When programming is complete, the status bits,

which indicate whether the program operation was

successful, should be checked. If bit 3 is set to a

“1,” then VPP was not within acceptable limits, and

the WSM did not execute the programming

sequence. If the program operation fails, Bit 4 of the

Status Register will be set within 3.3 ms as

determined by the timeout of the WSM.

The Status Register should be cleared before

attempting the next operation. Any CUI instruction

can follow after programming is completed;

however, reads from the Memory Array, Status

Register, or Intelligent Identifier cannot be

accomplished until the CUI is given the Read Array

command.

3.3.4

ERASE MODE

Erasure of a single block is initiated by writing the

Erase Setup and Erase Confirm commands to the

CUI, along with the addresses identifying the block

to be erased. These addresses are latched

internally when the Erase Confirm command is

issued. Block erasure results in all bits within the

block being set to “1.”

The WSM will execute a sequence of internally

timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are

sufficiently programmed to “0.”

3. Erase all bits within the block.

4. Verify that all bits within the block are

sufficiently erased.

While the erase sequence is executing, bit 7 of the

Status Register is a “0.”

When the Status Register indicates that erasure is

complete, the status bits, which indicate whether

the erase operation was successful, should be

checked. If the erase operation was unsuccessful,

bit 5 of the Status Register will be set to a “1,”

indicating an Erase Failure. If VPP was not within

A28F200BR

acceptable limits after the Erase Confirm command

is issued, the WSM will not execute an erase

sequence; instead, bit 5 of the Status Register is

set to a “1” to indicate an Erase Failure, and bit 3 is

set to a “1” to identify that VPP supply voltage was

not within acceptable limits.

The Status Register should be cleared before

attempting the next operation. Any CUI instruction

can follow after erasure is completed; however,

reads from the Memory Array, Status Register, or

Intelligent Identifier cannot be accomplished until

the CUI is given the Read Array command.

3.3.4.1

Suspending and Resuming Erase

Since an erase operation requires on the order of

seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in

order to read data from another block of the

memory. Once the erase sequence is started,

writing the Erase Suspend command to the CUI

requests that the WSM pause the erase sequence

at a pre-determined point in the erase algorithm.

The Status Register must then be read to determine

if the erase operation has been suspended.

At this point, a Read Array command can be written

to the CUI in order to read data from blocks other

than that which is being suspended. The only other

valid command at this time is the Erase Resume

command or Read Status Register command.

During erase suspend mode, the chip can go into a

pseudo-standby mode by taking CE# to VIH, which

reduces active current draw.

To resume the erase operation, the chip must be

enabled by taking CE# to VIL, then issuing the

Erase Resume command. When the Erase Resume

command is given, the WSM will continue with the

erase sequence and complete erasing the block. As

with the end of a standard erase operation, the

Status Register must be read, cleared, and the next

instruction issued in order to continue.

ADVANCE INFORMATION

17

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