AB28F800BR-B80 데이터 시트보기 (PDF) - Intel
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AB28F800BR-B80 Datasheet PDF : 36 Pages
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3.4.2
WP# = VIL FOR BOOT BLOCK
LOCKING
When WP# = VIL, the boot block is locked and any
program or erase operation will result in an error in
the Status Register. All other blocks remain
unlocked in this condition and can be programmed
or erased normally. Note that this feature is
overridden and the boot block unlocked when RP#
= VHH.
3.4.3
RP# = VHH OR WP# = VIH FOR BOOT
BLOCK UNLOCKING
Two methods can be used to unlock the boot block:
1. WP# = VIH
2. RP# = VHH
If both or either of these two conditions are met, the
boot block will be unlocked and can be
programmed or erased. The Truth Table, Table 8,
clearly defines the write protection methods.
Table 8. Write Protection Truth Table for
SmartVoltage Boot Block Family
VPP RP# WP# Write Protection
Provided
VIL
X
≥ VPPLK VIL
X All Blocks Locked
X All Blocks Locked
(Reset)
≥ VPPLK
≥ VPPLK
≥ VPPLK
VHH
VIH
VIH
X All Blocks Unlocked
VIL Boot Block Locked
VIH All Blocks Unlocked
3.5 Power Consumption
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the device is placed in the active mode.
Refer to the DC Characteristics table for ICC current
values.
3.5.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) is a low-power
feature during active mode of operation. The boot
block flash memory family incorporates Power
ADVANCE INFORMATION
A28F200BR
Reduction Control (PRC) circuitry which allows the
device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s
power consumption by entering the APS mode
where typical ICC current is less than 1 mA. The
device stays in this static state with outputs valid
until a new location is read.
3.5.3
STANDBY POWER
With CE# at logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode.
The standby operation disables much of the
device’s circuitry and substantially reduces device
power consumption. The outputs (DQ[0:15] or
DQ[0:7]) are placed in a high-impedance state
independent of the status of the OE# signal. When
CE# is at logic-high level during erase or program
functions, the devices will continue to perform the
erase or program function and consume erase or
program active power until erase or program is
completed.
3.5.4
DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low
typical ICC in deep power-down mode. The device
has a RP# pin which places the device in the deep
power-down mode. When RP# is at a logic-low
(GND ± 0.2V), all circuits are turned off in order to
save power. (Note: BYTE# pin must be at CMOS
levels to achieve the most deep power-down
current savings.)
During read modes, the RP# pin going low de-
selects the memory and places the output drivers in
a high impedance state. Recovery from the deep
power-down state, requires a minimum access time
of tPHQV. (See the AC Characteristics table for
specification numbers.)
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has
been corrupted by the RP# function. As in the read
mode above, all internal circuitry is turned off to
achieve the power savings.
RP# transitions to VIL, or turning power off to the
device will clear the Status Register.
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