MC145201F 데이터 시트보기 (PDF) - Motorola => Freescale

부품명

상세내역

제조사

MC145201F

2.0 GHz PLL Frequency Synthesizers

Motorola => Freescale 

THRESHOLD

+5 V

DETECTOR

1 REFout

REFin 20

INTEGRATOR

OPTIONAL LOOP

ERROR SIGNALS

(NOTE 1)

+V

LOW–PASS

FILTER

2 LD

3 φR

4 φV

5 VPD

6 PDout

7

GND

Din 19

CLK 18

ENB 17

OUTPUT A 16

15

OUTPUT B

VDD 14

MCU

GENERAL–PURPOSE

DIGITAL OUTPUT

+5 V

8

Rx

9

NC TEST 1

TEST 2 13 NC

VCC 12

Q1

NOTE 2

10 fin

fin 11

1000 pF

UHF

VCO

BUFFER

UHF OUTPUT

NOTES:

1. When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–

Locked Loop — Low–Pass Filter Design page for additional information.

2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section of

the device to be shut down via use of the general–purpose digital pin, OUTPUT B. If the standby

feature is not needed, tie Pin 12 directly to the power supply.

3. For optimum performance, bypass the VCC, VDD, and VPD pins to GND with low–inductance ca-

pacitors.

4. The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution

required for the VCO. Also, the VCO frequency divided by fR = NT = N × 64 + A; this determines

the values (N, A) that must be programmed into the N and A counters, respectively.

Figure 22. Example Application

DEVICE #1

OUTPUT A

Din

CLK ENB (DATA OUT)

DEVICE #2

OUTPUT A

Din

CLK ENB (DATA OUT)

CMOS

MCU

OPTIONAL

NOTE: See related Figures 24 through 26; these bit streams apply to the MC145190, MC145191, MC145200,

and MC145201.

Figure 23. Cascading Two Devices

MOTOROLA

MC145200•MC145201

19

Share Link: