21555 데이터 시트보기 (PDF) - Intel
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21555 Datasheet PDF : 60 Pages
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Table 10. 33 MHz PCI Signal Timing Specifications
Symbol Parameter
Minimum Maximum Unit
Tval
Tval(ptp)
Ton
Toff
Tsu
Tsu(ptp)
Th
CLK to signal valid delay — bused signalsa,b,c
CLK to signal valid delay — point-to-pointa,b,c
Float to active delaya,b
Active to float delaya,b
Input setup time to CLK — bused signalsa,b,c
Input setup time to CLK—point-to-pointa,b,c
Input signal hold time from CLKa,b
2
11
ns
2
12
ns
2
—
ns
—
28
ns
7
—
ns
10, 12
—
ns
0
—
ns
a. See Figure 5.
b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.
c. Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64,
p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par,
s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
Table 11. 66 MHz PCI Signal Timing Specifications
Symbol Parameter
Minimum Maximum Unit
Tval
Tval(ptp)
Ton
Toff
Tsu
Tsu(ptp)
Th
CLK to signal valid delay — bused signalsa,b,c
CLK to signal valid delay — point-to-pointa,b,c
Float to active delaya,b
Active to float delaya,b
Input setup time to CLK — bused signalsa,b
Input setup time to CLK—point-to-pointa,b
Input signal hold time from CLKa,b
2
6
ns
2
6
ns
2
—
ns
—
14
ns
3
—
ns
5
—
ns
0
—
ns
a. See Figure 5.
b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.
c. Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64,
p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par,
s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
3.4.3
Reset Timing Specifications
Table 12 shows the reset timing specifications for p_rst_l and s_rst_l.
Table 12. Reset Timing Specifications (Sheet 1 of 2)
Symbol
Trst
Trst-clk
Trst-off
Tsrst
Tsrst-on
Tdsrst
–
Parameter
p_rst_l active time after power stable
p_rst_l active time after p_clk stable
p_rst_l active-to-output float delay
s_rst_l active after p_rst_l assertion
s_rst_l active time after s_clk stable
s_rst_l deassertion after p_rst_l deassertion
p_rst_l slew ratea
Minimum Maximum Unit
1
—
100
—
—
40
—
40
100
—
0
25
50
—
µs
µs
ns
ns
µs
Cycles
mV/ns
26
Datasheet
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