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CA16B2CAA

CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Functional Description

Receiver

The optical receiver in the CA16-type transponder has an

APD and is optimized for the particular SDH/SONET

application segment in which it was designed to operate.

The detected serial data output of the optical receiver is

connected to a clock and data recovery circuit (CDR),

which extracts a 2488.32 MHz clock signal. This recov-

ered serial bit clock signal and a retimed serial data signal

are presented to the 16-bit serial-to-parallel converter and

to the frame and byte detection logic.

The serial-to-parallel converter consists of three 16-bit

registers. The first is a serial-in parallel-out shift register,

which performs serial-to-parallel conversion. The second

is an internal 16-bit holding register, which transfers data

from the serial-to-parallel register on byte boundaries as

determined by the frame and byte detection logic. On the

falling edge of the free-running POCLK signal, the data in

the holding register is transferred to the output holding

register where it becomes available as RxQ[0:15].

Note: Future versions of the cooled transponder will

not support the frame-detect function.

The frame and byte boundary detection circuitry searches

the incoming data for three consecutive A1 bytes followed

immediately by an A2 byte. Framing pattern detection is

enabled and disabled by the FRAMEN input. The frame

detection process is started by a rising edge on OOF

while FRAMEN is active (FRAMEN = high). It is disabled

when a framing pattern is detected. When framing pattern

detection is enabled (FRAMEN = high), the framing pat-

tern is used to locate byte and frame boundaries in the

incoming serial data stream from the CDR circuits. During

this time, the parallel output data bus (RxQ[0:15]) will not

contain valid data. The timing generator circuitry takes the

located byte boundary and uses it to block the incoming

serial data stream into bytes for output on the parallel out-

put data bus (RxQ[0:15]). The frame boundary is reported

on the framing pulse (FP) output when any 32-bit pattern

matching the framing pattern is detected in the incoming

serial data stream. When framing detection is disabled

(FRAMEN = low), the byte boundary is fixed at the loca-

tion found when frame detection was previously enabled.

Transmitter

The optical transmitter in the CA16-type transponder is

optimized for the particular SDH/SONET segment in

which it is destined to operate. The transmitter has a

cooled DFB laser as the optical element and operates at a

nominal 1550 nm (45 standard ITU wavelengths are avail-

able for DWDM applications). Under user control, the

transmitter can switch to either one of two adjacent ITU

wavelengths (100 GHz spacing). The transmitter is driven

122

by a serial data stream developed in the parallel-to-serial

conversion logic and by a 2488.32 MHz serial bit clock sig-

nal synthesized from the 155.52 MHz TXREFCLK input.

Note that the clock divider and phase-detect circuitry

shown in Figure 1 generates internal reference clocks and

timing functions for the transmitter. Therefore, it is impor-

tant that the TxREFCLK input is generated from a precise

and stable source. To prevent internal timing signals from

producing jitter in the transmitted serial data that exceeds

the SDH/SONET jitter generation requirements of 0.01 UI,

it is required that the TxREFCLK input be generated from a

crystal oscillator or other source having a frequency accu-

racy better than 20 ppm. In order to meet the SDH/

SONET jitter generation requirement, the reference clock

jitter must be guaranteed to be less than 1 ps rms over the

12 kHz to 20 MHz bandwidth. When used in SONET net-

work applications, this input clock must be derived from a

source that is synchronized to the primary reference clock.

The timing generation circuitry provides two separate

functions. It develops a byte rate clock that is synchro-

nized to the 2488.32 MHz transmit serial clock, and it pro-

vides a mechanism for aligning the phase between the

incoming byte clock (PICLK) and the clock that loads the

parallel data from the input register into the parallel-to-

serial shift register.

The PCLK output is a byte rate (155 MHz) version of the

serial transmit clock and is intended for use by upstream

multiplexing and overhead processing circuits. Using

PCLK for upstream circuits will ensure a stable frequency

and phase relationship between the parallel data coming

into the transmitter and the subsequent parallel-to-serial

timing functions. In the parallel-to-serial conversion pro-

cess, the incoming data is passed from the PICLK byte

clock timing domain to the internally generated byte clock

timing domain that is phase aligned to the internal serial

transmit clock. The timing generator also produces a feed-

back reference clock to the phase detector. A counter

divides the synthesized clock down to the same frequency

as the reference clock TxREFCLK.

The parallel-to-serial converter shown in Figure 1 is com-

prised of an FIFO and a parallel-to-serial register. The

FIFO input latches the data from the TxD[0:15]P/N bus on

the rising edge of PICLK. The parallel-to-serial register is a

loadable shift register that takes parallel input from the

FIFO output. An internally generated divide-by-16 clock,

which is phase aligned to the transmit serial clock, as

described above, activates the parallel data transfer

between registers. The serial data is shifted out of the par-

allel-to-serial register at the transmit serial clock rate.

Agere Systems Inc.

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