CA16B2CNN 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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CA16B2CNN

CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Transmitter Data Input Timing (continued)

Input Timing Mode 2

To avoid the loss of data, idle or dummy bytes should

be sent on the TXD[0:15] bus whenever PHERR goes

high. In the configuration shown in Figure 6, the

PHERR signal is used as an input to the customer

logic. Upon detecting a high on the PHERR signal, the

customer logic should return a high signal, one that

remains high for at least two byte-clock cycles, to the

PHINIT input of the CA16. Also, when PHERR goes

high, the customer logic should start sending idle or

dummy bytes to the CA16 on the TXD[0:15] bus. This

should continue until PHERR goes low.

The FIFO is initialized two-to-eight byte clocks after

PHINIT goes high for two byte clocks. PHERR goes low

after the FIFO is initialized. Upon detecting a low on

PHERR, the customer logic can start sending real data

bytes on TXD[0:15]. The two timing loops (PCLK to

PICLK and PHERR to PHINIT) do not have to be of

equal length.

OSCILLATOR

155.52 MHz ± 20 ppm

CLOCK

16

DATA

D

Q

CUSTOMER LOGIC

PCLK

TXREFCLK

DIVIDER

PLL

PICLK

INTERNAL

PCLK

TXD[0:15]

TIMING

GENERATOR

FIFO

PHERR

PHINIT

CENTERS

FIFO

LOCKDET

CA16 TRANSPONDER

Figure 6. Block Diagram Timing Mode 2

1121(F).b

200

Agere Systems Inc.

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