TSA5055T 데이터 시트보기 (PDF) - Philips Electronics
부품명
상세내역
제조사
TSA5055T Datasheet PDF : 20 Pages
| |||
Philips Semiconductors
2.65 GHz bidirectional I2C-bus controlled
synthesizer
Product specification
TSA5055T
Table 1 Write data format; see notes 1 to 13
BYTE
MSB
DATA BYTE
Address
1
1
0
0
0 MA1
Programmable divider
0 N14 N13 N12 N11 N10
N7 N6 N5 N4 N3 N2
Charge-pump and test bits
1
CP
T1
T0
1
1
Output ports, control bits
P7 P6 P5 P4 P3
X
Notes
1. MA1 and MA0: programmable address bits (see Table 3).
2. A: Acknowledge bit.
3. N14 to N0: programmable divider bits.
4. N = N14 × 214 + N13 × 213 + ... + N1 × 21 + N0.
5. CP: charge-pump current. CP = 0: 50 µA; CP = 1: 220 µA.
6. P7 to P4 = 1: open-collector outputs are active.
7. P7 to P3 and P0 = 0: outputs are in high-impedance state.
8. P3 and P0 = 1: current-limited outputs are active.
9. T1, T0 and OS = 0, 0 and 0: normal operation.
10. T1 = 1: P6 = fREF and P7 = fDIV.
11. T0 = 1: 3-state charge-pump.
12. OS = 1: Operational amplifier output is switched off (varicap drive disable).
13. X: don’t care.
MA0
N9
N1
1
X
LSB
0
N8
N0
OS
P0
COMMAND
A byte 1
A byte 2
A byte 3
A byte 4
A byte 5
READ mode: R/W = 1; see Table 2
Data can be read out of the TSA5055T by setting the R/W
bit to 1. After the slave address has been recognized, the
TSA5055T generates an Acknowledge signal (A) and the
first data byte (status byte) is transferred to the SDA line
(MSB first). Data is valid on the SDA line while the SCL
clock signal is HIGH.
A second data byte can be read out of the TSA5055T if the
processor generates an Acknowledge signal on the SDA
line. End of transmission will occur if the processor does
not send an Acknowledge signal.
The TSA5055T will then release the data line to allow the
processor to generate a STOP condition. When ports
P3 to P7 are used as inputs, they must be programmed to
their high-impedance state.
The POR flag (Power-On Reset) is set to 1 at power-on
and when VCC goes below 3 V. The flag is reset when an
end of data is detected by the TSA5055T (end of a READ
sequence). Control of the loop is made possible with the
in-lock flag FL, which indicates when the loop is
phase-locked (FL = 1).
1999 Aug 11
5
Share Link: 