TSA5055T 데이터 시트보기 (PDF) - Philips Electronics

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TSA5055T

2.65 GHz bidirectional I2C-bus controlled synthesizer

Philips Electronics 

Philips Semiconductors

2.65 GHz bidirectional I2C-bus controlled

synthesizer

Product specification

TSA5055T

Table 2 Read data format (see notes 1 to 5)

BYTE

Address

Status byte

MSB

1

1

POR FL

DATA BYTE

LSB

0

0

0 MA1 MA0 1

I2

I1

I0

A2 A1 A0

Notes

1. POR: Power-on reset flag (POR = 1 on power-on).

2. FL: in-lock flag (FL = 1 when the loop is phase-locked).

3. I2, I1 and I0: digital information for I/O ports P7, P5 and P4 respectively.

4. A2, A1 and A0: digital outputs of the 5-level ADC. Accuracy is 1⁄2 LSB (see Table 4).

5. MSB is transmitted first.

COMMAND

A byte 1

− byte 2

Bits I2, I1 and I0 represent the status of the I/O ports P7, P5 and P4, respectively. A logic ‘0’ indicates a LOW level and

a logic ‘1’ a HIGH level (TTL levels). A built-in 5-level ADC is available at I/O port P6. This ADC can be used to feed AFC

information to the controller from the IF section of the receiver, as shown in Fig.4. The relationship between bits A2, A1,

A0 and the input voltage at port P6 is given in Table 4.

Table 3 Address selection

MA1

0

0

1

1

MA0

0

1

0

1

0 to 0.1VCC

always valid

0.4VCC to 0.6VCC

0.9VCC to 13.5 V

VOLTAGE APPLIED ON PORT P3

Address selection; see Table 3

The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having several

synthesizers (up to three) in one system. The relationship between MA1 and MA0 and the input voltage at port P3 is

given in Table 3.

Table 4 ADC levels

A2

A1

A0

VOLTAGE APPLIED ON PORT P6

1

0

0

0.6VCC to VCC

0

1

1

0.45VCC to 0.6VCC

0

1

0

0.3VCC to 0.45VCC

0

0

1

0.15VCC to 0.3VCC

0

0

0

0 to 0.15VCC

1999 Aug 11

6

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