MT28C3212P2NFL 데이터 시트보기 (PDF) - Micron Technology
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MT28C3212P2NFL Datasheet PDF : 47 Pages
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
low-order I/O pins (DQ0–DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.
Register data is updated and latched on the rising
edge of F_OE# or F_CE#, whichever occurs first. The
latest falling edge of either of these two signals up-
dates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 9 defines the sta-
tus register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for the commands
listed in Table 4. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 5 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when VPP is within its correct volt-
age range.
Table 5
Command Definitions
COMMAND
READ ARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME - ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
FIRST BUS CYCLE
OPERATION ADDRESS DATA
WRITE
WA
FFh
WRITE
IA
90h
WRITE
BA
70h
WRITE
BA
50h
WRITE
QA
98h
WRITE
BA
20h
WRITE
WA
40h/10h
WRITE
BA
B0h
WRITE
BA
D0h
WRITE
BA
60h
WRITE
BA
60h
WRITE
BA
60h
WRITE
PA
C0h
WRITE
LPA
C0h
SECOND BUS CYCLE
OPERATION ADDRESS DATA
READ
IA
ID
READ
BA
SRD
READ
QA
QD
WRITE
BA
D0h
WRITE
WA
WD
WRITE
BA
01h
WRITE
BA
D0h
WRITE
BA
2Fh
WRITE
PA
PD
WRITE
LPA
FFFDh
NOTE: 1. WA: Word address of memory location to be written, or read
2. IA: Identification code address
3. BA: Address within the block
4. ID: Identification code data
5. SRD: Data read from the status register
6. QA: Query code address
7. QD: Query code data
8. WD: Data to be written at the location WA
9. PA: Protection register address
10. LPA: Lock protection register address
11. PD: Protection register data
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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