MT28C3212P2NFL-10B 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT28C3212P2NFL-10B

FLASH AND SRAM COMBO MEMORY

Micron Technology 

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the VPP status bit (SR3), the pro-

gram status bit (SR4), and the erase status bit (SR5) of

the status register. The CLEAR STATUS REGISTER com-

mand (50h) allows the external microprocessor to clear

these status bits and synchronize to the internal op-

erations. When the status bits are cleared, the device

returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-

ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0–DQ7. Control pins F_CE# and F_OE# must

be at a logic LOW level (VIL), and F_WE# and F_RP#

must be at a logic HIGH level (VIH) to read data from the

array. Data is available on DQ0–DQ15. Any valid ad-

dress within any of the blocks selects that address and

allows data to be read from that address. Upon initial

power-up, the device defaults to the read array mode.

READ CHIP PROTECTION IDENTIFICATION DATA

The chip identification mode outputs three types

of information: the manufacturer/device identifier, the

block locking status, and the protection register. Two

bus cycles are required for this operation: the chip iden-

tification data is read by entering the command code

90h on DQ0–DQ7 to the bank containing address 00h

and the identification code address on the address

lines. Control pins F_CE# and F_OE# must be at a logic

LOW level (VIL), and F_WE# and F_RP# must be at a

logic HIGH level (VIH) to read data from the protection

configuration register. Data is available on DQ0–DQ15.

After data is read from the protection configuration

register, the READ ARRAY command, FFh, must be is-

sued to the bank containing address 00h prior to issu-

ing other commands. See Table 11 for further details.

READ QUERY

The read query mode outputs common Flash inter-

face (CFI) data when the device is read (see Table 15).

Two bus cycles are required for this operation. It is

possible to access the query by writing the read query

command code 98h on DQ0–DQ7. Control pins F_CE#

and F_OE# must be at a logic LOW level (VIL), and F_WE#

and F_RP# must be at a logic HIGH level (VIH) to read

data from the query. The CFI data structure contains

information such as block size, density, command set,

and electrical specifications. To return to read array

mode, write the read array command code FFh on DQ0–

DQ7.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0–DQ7. Two bus cycles are required for

this operation: one to enter the command code and a

second to read the status register. In a READ cycle, the

address is latched and register data is updated on the

falling edge of F_OE# or F_CE#, whichever occurs last.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

15

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

Share Link: