MT28C3212P2FL-10B 데이터 시트보기 (PDF) - Micron Technology

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MT28C3212P2FL-10B

FLASH AND SRAM COMBO MEMORY

Micron Technology 

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

Table 9

Status Register Bit Definition

WSMS

ESS

ES

PS

VPPS

PSS

BLS

R

7

6

5

4

3

2

1

0

STATUS

BIT # STATUS REGISTER BIT

DESCRIPTION

SR7 WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word

1 = Ready

program or block erase completion, before checking

0 = Busy

program or erase status bits.

SR6 ERASE SUSPEND STATUS (ESS)

1 = BLOCK ERASE Suspended

0 = BLOCK ERASE in

Progress/Completed

When ERASE SUSPEND is issued, WSM halts execution and

sets both WSMS and ESS bits to “1.” ESS bit remains set to

“1” until an ERASE RESUME command is issued.

SR5 ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful BLOCK ERASE

When this bit is set to “1,” WSM has applied the maximum

number of erase pulses to the block and is still unable to

verify successful block erasure.

SR4 PROGRAM STATUS (PS)

1 = Error in PROGRAM

0 = Successful PROGRAM

When this bit is set to “1,” WSM has attempted but failed to

program a word.

SR3 VPP STATUS (VPPS)

The VPP status bit does not provide continuous indication

1 = VPP Low Detect, Operation Abort of the VPP level. The WSM interrogates the VPP level only

0 = VPP = OK

after the program or erase command sequences have been

entered and informs the system if VPP has not been switched

on. The VPP level is also checked before the PROGRAM/ERASE

operation is verified by the WSM. The MT28C3212P2NFL

device allows PROGRAM or ERASE at 0V, in which case SR3 is

held at “0.”

SR2 PROGRAM SUSPEND STATUS (PSS)

When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended

and sets both WSM and PSS bits to “1.” PSS bit remains set to

0 = PROGRAM in Progress/Completed “1” until a PROGRAM RESUME command is issued.

SR1 BLOCK LOCK STATUS (BLS)

If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted specified is aborted, and the device is returned to read status

0 = No Operation to Locked Blocks

mode.

SR0 RESERVED FOR FUTURE

ENHANCEMENT

This bit is reserved for future.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

21

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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