73S8009C 데이터 시트보기 (PDF) - Teridian Semiconductor Corporation
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73S8009C Datasheet PDF : 33 Pages
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73S8009C Data Sheet
DS_8009C_025
3.4 System Controller Interface
Four separate digital inputs and two outputs allow direct control of the card interface from the host:
Pin CS: Chip select control.
Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence.
Pin RSTIN: controls the card RST signal.
Pin RDY: Indicates when smart card power supply is stable and ready.
Pin OFF: Indicator of card presence and any card fault conditions.
Interrupt output to the host: When the card is not activated, the OFF pin informs the host about the card
presence only (Low = No card in the reader, high = card inserted). When CMDVCC (#/% signals) is/are
set low (card activation sequence requested from the host), low level on OFF means a fault has been
detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that
automatically initiates a deactivation sequence. The smart card pass through signals are enabled when
the RDY conditions are met.
3.5 Card Power Supply and Voltage Supervision
The 73S8009C smart card interface IC incorporates an LDO voltage regulator for the card power supply,
VCC (VP to VCC conversion uses an internal LDO). The voltage output is controlled by the digital input
sequence of CMDVCC# and CMDVCC%. This regulator is able to provide 1.8V, 3V or 5V card voltage
sourced from the VP power supply. Internal digital circuitry is also powered by the VP power supply
(except for the ON/OFF circuitry which is powered from VPC). . A card deactivation sequence is forced
upon fault detected by an overcurrent condition or card removal event. The voltage regulator can provide
a card current of 65 mA in compliance with EMV 4.1 for 3-V and 5-V cards and 40 mA for 1.8 V cards.
The signals CMDVCC# and CMDVCC% control the turn-on, output voltage value, and turn-off of VCC.
When either signal is asserted low, VCC will ramp to the selected value or if both signals are asserted low
(within 400ns of each other), VCC will ramp to 1.8V. These signals are edge triggered. If CMDVCC% is
asserted low (to command VCC to be 5V) and at a much later time (greater than 2 µs, typically),
CMDVCC# is asserted low, it will be ignored (and vice versa.)
At the assertion (low) of either or both CMDVCC (#/% signals), VCC will rise to the requested value. When
VCC rises to an acceptable value, and stays above that value for approximately 20 µs, RDY will be set
high. Approximately 510 µs after the fall of CMDVCC (#/%), the circuit will check the see if VCC is at or
above the required minimum value (indicated by RDY=1) and if not, will begin an emergency deactivation
sequence. During the 510 µs time, card removal, or de-assertion of CMDVCC (#/%) shall also initiate an
emergency deactivation sequence. The circuit provides over-current protection and limits Icc to 150 mA,
maximum for self-protection. When an over-current condition is sensed, the circuit will invoke a
de-activation sequence.
20
Rev. 1.4
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