74LV132DB(2015) 데이터 시트보기 (PDF) - NXP Semiconductors.

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74LV132DB
(Rev.:2015)

Quad 2-input NAND Schmitt trigger

NXP Semiconductors. 

Nexperia

6. Pinning information

6.1 Pinning

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Fig 4. Pin configuration SO14 and (T)SSOP14

6.2 Pin description

Table 2.

Symbol

1A to 4A

1B to 4B

1Y to 4Y

GND

VCC

Pin description

Pin

1, 4, 9, 12

2, 5, 10, 13

3, 6, 8, 11

7

14

7. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

nA

nB

L

L

L

H

H

L

H

H

74LV132

Quad 2-input NAND Schmitt trigger

74LV132

terminal 1

index area

1B 2

1Y 3

2A 4

2B 5

2Y 6

VCC(1)

13 4B

12 4A

11 4Y

10 3B

9 3A

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Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to VCC.

Fig 5. Pin configuration DHVQFN14

Description

data input

data input

data output

ground (0 V)

supply voltage

Output

nY

H

H

H

L

74LV132

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 9 December 2015

© Nexperia B.V. 2017. All rights reserved

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