87C524 데이터 시트보기 (PDF) - Philips Electronics

부품명

상세내역

제조사

87C524

80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer

Philips Electronics 

Philips Semiconductors

80C51 8-bit microcontrollers

16K/32K, 512 OTP, I2C, watchdog timer

Product specification

87C524/87C528

AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE

SYMBOL

PARAMETER

INPUT

OUTPUT

I2C SPECIFICATION

SCL TIMING CHARACTERISTICS

tHD;STA

START condition hold time

tLOW

SCL LOW time

tHIGH

SCL HIGH time

tRC

SCL rise time

tFC

SCL fall time

SDA TIMING CHARACTERISTICS

≥ 14 tCLCL1

≥ 16 tCLCL

≥ 14 tCLCL1

≤ 1µs1

≤ 0.3µs1

Note 2

Note 2

≥ 80 tCLCL3

Note 5

≤ 0.3µs6

≥ 4.0µs

≥ 4.7µs

≥ 4.0µs

≤ 1.0µs

≤ 0.3µs

tSU;DAT1 Data set-up time

≥ 250ns

Note 2

≥ 250ns

tHD;DAT

Data hold time

≥ 0ns

Note 2

≥ 0ns

tSU;STA

Repeated START set-up time

≥ 14 tCLCL1

Note 2

≥ 4.7µs

tSU;STO STOP condition set-up time

≥ 14 tCLCL1

Note 2

≥ 4.0µs

tBUF

Bus free time

≥ 14 tCLCL1

Note 2

≥ 4.7µs

tRD

SDA rise time

≤ 1µs4

Note 5

≤ 1.0µs

tFD

SDA fall time

≤ 0.3µs4

≤ 0.3µs 6

≤ 0.3µs

NOTES:

1. At fCLK = 3.5MHz, this evaluates to 14 × 286ns = 4µs, i.e., the bit-level I2C interface can respond to the I2C protocol for fCLK ≥ 3.5 MHz.

2. This parameter is determined by the user software, it has to comply with the I2C.

3. This value gives the autoclock pulse length which meets the I2C specification for the specified XTAL clock frequency range. Alternatively, the

SCL pulse may be timed by software.

4. Spikes on SDA and SCL lines with a duration of less than 4 × fCLK will be filtered out.

5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs.

6. The maximum capacitance on bus lines SDA and SCL is 400pF.

1999 Jul 23

13

Share Link: