87C524 데이터 시트보기 (PDF) - Philips Electronics

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87C524

80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer

Philips Electronics 

Philips Semiconductors

80C51 8-bit microcontrollers

16K/32K, 512 OTP, I2C, watchdog timer

Product specification

87C524/87C528

Additionally, if acting as master:

– generating START and STOP conditions

– handling bus arbitration

– generating serial clock pulses if S1BIT is not used.

Three SFRs control the bit-level I2C interface: S1INT, S1BIT and

S1SCS.

INTERRUPT SYSTEM

The interrupt structure of the 8XC528 is the same as that used in the

80C51, but includes two additional interrupt sources: one for the

third timer/counter, T2, and one for the I2C interface. The interrupt

enable and interrupt priority registers are IE and IP.

IE: Interrupt Enable Register

This register is located at address A8H. Refer to Table 3.

IE SFR (A8H)

7

6

5

4

3

2

1

0

EA ES1 ET2 ES ET1 EX1 ET0 EX0

IP: Interrupt Priority Register

This register is located at address B8H. Refer to Table 4.

IP SFR (B8H)

7

6

5

4

3

2

1

0

– PS1 PT2 PS PT1 PX1 PT0 PX0

Table 3. Description of IE Bits

MNEMONIC

BIT

FUNCTION

EA

IE.7

General enable/disable control:

0 = NO interrupt is enabled.

1 = ANY individually enabled interrupt will be accepted.

ES1

IE.6

Enable bit-level I2C I/O interrupt

ET2

IE.5

Enable Timer 2 interrupt

ES

IE.4

Enable Serial Port interrupt

ET1

IE.3

Enable Timer 1 interrupt

EX1

IE.2

Enable External interrupt 1

ET0

IE.1

Enable Timer 0 interrupt

EX0

IE.0

Enable External interrupt 0

Table 4. Description of IP Bits

MNEMONIC

BIT

FUNCTION

–

IP.7

Reserved.

PS1

IP.6

Bit-level I2C interrupt priority level

PT2

IP.5

Timer 2 interrupt priority level

PS

IP.4

Serial Port interrupt priority level

PT1

IP.3

Timer 1 interrupt priority level

PX1

IP.2

External Interrupt 1 priority level

PT0

IP.1

Timer 0 interrupt priority level

PX0

IP.0

External Interrupt 0 priority level

The interrupt vector locations and the interrupt priorities are:

Source

Vector

0003H

002BH

0053H

000BH

0013H

001BH

0023H

Address

IE0

TF2+EXF2

SI (I2C)

TF0

IE1

TF1

RI+TI

Priority within Level

Highest

Lowest

1999 Jul 23

9

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