P89C535 데이터 시트보기 (PDF) - Philips Electronics
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P89C535 Datasheet PDF : 35 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
Preliminary specification
89C535/89C536/89C538
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
VARIABLE CLOCK
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN MAX UNIT
1/tCLCL
9
Oscillator frequency
Speed versions : N (33MHz)
3.5
33
MHz
3.5
33
tLHLL
9
tAVLL
9
tLLAX
9
tLLIV
9
tLLPL
9
tPLPH
9
tPLIV
9
tPXIX
9
tPXIZ
9
tAVIV
9
tPLAZ
9
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2tCLCL–40
21
tCLCL–25
5
tCLCL–25
5
4tCLCL–65
tCLCL–25
5
3tCLCL–45
45
3tCLCL–60
0
0
tCLCL–25
5tCLCL–80
10
ns
ns
ns
55
ns
ns
ns
30
ns
ns
5
ns
70
ns
10
ns
tRLRH
10, 11
tWLWH
10, 11
tRLDV
10, 11
tRHDX
10, 11
tRHDZ
10, 11
tLLDV
10, 11
tAVDV
10, 11
tLLWL
10, 11
tAVWL
10, 11
tQVWX
10, 11
tWHQX
10, 11
tQVWH
11
tRLAZ
10, 11
tWHLH
10, 11
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6tCLCL–100
82
6tCLCL–100
82
5tCLCL–90
0
0
2tCLCL–28
8tCLCL–150
9tCLCL–165
3tCLCL–50
3tCLCL+50
40
4tCLCL–75
45
tCLCL–30
0
tCLCL–25
5
7tCLCL–130
80
0
tCLCL–25
tCLCL+25
5
ns
ns
60
ns
ns
32
ns
90
ns
105
ns
140
ns
ns
ns
ns
ns
0
ns
55
ns
tCHCX
13
tCLCX
13
tCLCH
13
tCHCL
13
Shift Register
High time
Low time
Rise time
Fall time
17
tCLCL–tCLCX
ns
17
tCLCL–tCHCX
ns
5
ns
5
ns
tXLXL
12
Serial port clock cycle time
12tCLCL
360
ns
tQVXH
12
Output data setup to clock rising edge
10tCLCL–133
167
ns
tXHQX
12
Output data hold after clock rising edge
2tCLCL–80
50
ns
tXHDX
12
Input data hold after clock rising edge
0
0
ns
tXHDV
12
Clock rising edge to input data valid
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
1997 Jun 05
18
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