Figure 20: A/A Mux Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence
Address
5555
2AAA
5555
5555
2AAA
5555
R/C
OE
WE
High-Z
I/O7-I/O0
TWP TWPH
AA
55
80
AA
55
10
A49FL004
TSCE
Chip Erase Command Input
Chip Erase Operation In Progress
Figure 21: A/A Mux Mode Product ID Entry and Read Timing Diagram
Three-Byte Product ID Entry
Command Sequence
Address
5555
2AAA
5555
0000
0001
0003
R/C
OE
WE
High-Z
I/O7-I/O0
TWP TWPH
TIDA
AA
55
90
TAA
37
95
7F
Figure 22: A/A Mux Mode Product ID Exit and Reset Timing Diagram
Three-Byte Product ID Exit and
Reset Command Sequence
Address
5555
2AAA
5555
R/C
OE
WE
High-Z
I/O7-I/O0
TWP TWPH
AA
55
F0
PRELIMINARY (September, 2005, Version 0.0)
28
AMIC Technology, Corp.