5962-9755701HXA 데이터 시트보기 (PDF) - Avago Technologies

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5962-9755701HXA

Hermetically Sealed Analog Isolation Amplifi er

Avago Technologies 

Shunt Resistor Selections

The current-sensing shunt resistor should have low re-

sistance (to minimize power dissipation), low inductance

(to minimize di/dt induced voltage spikes which could

adversely affect operation), and reasonable tolerance (to

maintain overall circuit accuracy). The value of the shunt

should be chosen as a compromise between minimizing

power dissipation by making the shunt resistance smaller

and improving circuit accuracy by making it larger and

utilizing the full input range of the HCPL-7850. Avago

Technologies recommends four different shunts which

can be used to sense average currents in motor drives up

to 35 A and 35 hp. Table 1 shows the maximum current

and horsepower range for each of the LVR-series shunts

from Dale. Even higher currents can be sensed with lower

value shunts available from vendors such as Dale, IRC,

and Isotek (Isabellenhuette). When sensing currents large

enough to cause significant heating of the shunt, the tem-

perature coefficient of the shunt can introduce nonlinear-

ity due to the signal dependent temperature rise of the

shunt. Using a heat sink for the shunt or using a shunt with

a lower tempco can help minimize this effect. The Appli-

cation Note 1078, Designing with Avago Technologies

Isolation Amplifiers, contains additional information on

designing with current shunts.

The recommended method for connecting the isolation

amplifier to the shunt resistor is shown in Figure 24. Pin 2

(VIN+) is connected to the positive terminal of the shunt

resistor, while pin 3 (VIN–) is shorted to pin 4 (GND1), with

the power-supply return path functioning as the sense

line to the negative terminal of the current shunt. This

allows a single pair of wires or PC board traces to connect

the isolation amplifier circuit to the shunt resistor. In

some applications, however, supply currents flowing

through the power-supply return path may cause offset

or noise problems. In this case, better performance may

be obtained by connecting pin 3 to the negative terminal

of the shunt resistor separate from the power supply

return path. When connected this way, both input pins

should be bypassed. Whether two or three wires are used,

it is recommended that twisted-pair wire or very close PC

board traces be used to connect the current shunt to the

isolation amplifier circuit to minimize electromagnetic in-

terference to the sense signal.

The 68  resistor in series with the input lead forms a

low-pass anti-aliasing filter with the input bypass capacitor

with a 200 kHz bandwidth. The resistor performs another

important function as well; it dampens any ringing which

might be present in the circuit formed by the shunt, the

input bypass capacitor, and the wires or traces connect-

ing the two. Undampened ringing of the input circuit near

the input sampling frequency can alias into the baseband

producing what might appear to be noise at the output

of the device. To be effective, the damping resistor should

be at least 39 .

PC Board Layout

In addition to affecting offset, the layout of the PC board

can also affect the common mode rejection (CMR) per-

formance of the isolation amplifier, due primarily to stray

capacitive coupling between the input and the output

circuits. To obtain optimal CMR performance, the layout

of the printed circuit board (PCB) should minimize any

stray coupling by maintaining the maximum possible

distance between the input and output sides of the circuit

and ensuring that any ground plane on the PCB does not

pass directly below the HCPL-7850. Using surface mount

components can help achieve many of the PCB objec-

tives discussed in the preceding paragraphs. An example

through-hole PCB layout illustrating some of the more

important layout recommendations is shown in Figures

26 and 27. See Applications Note 1078, Designing with

Avago Technologies Isolation Amplifiers, for more infor-

mation on PCB layout consideration.

1

VDD

2

+

1 k VIN+

3

–

VIN–

4

GND

27 :

8

VDD 1 k

+

7

VOUT+ 1 k

–

6

VOUT–

5

GND

0.1 PF

(+) VDD

(–) 5.5 VDC

CONDITIONS: ICC = 17.5 mA

TA = +125° C

Figure 28. Operating Circuit for Burn-In and Steady State Life Tests.

14

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