ACPL-M61L-560E 데이터 시트보기 (PDF) - Avago Technologies
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ACPL-M61L-560E Datasheet PDF : 16 Pages
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Glitch Free Power-up and Power-Down Feature.
Upon Powering-up or Powering-down of the optocoupler,
glitches produced in the output are undesirable. Glitches
can lead to false data in the optocoupler application.
ACPL-x6xL has a feature that holds the output in a known
state until VDD is at a safe level. Figure 13 and 14 show
typical output waveforms during Power-up and Power-
down process.
Slew-rate controlled outputs Feature
Typically, the output slew rate (rise and fall time) will vary
with the output load, as more time is needed to charge up
the higher load. The propagation delay and the PWD will
increase with the load capacitance. This will be an issue
especially in parallel communication because different
communication line will have different load capacitances.
However, Avago’s new optocoupler ACPL-x6xL has built in
slew-rate controlled feature, to ensure that the output rise
and fall time remain stable across wide load capacitance.
Figure 15 shows the rise time and fall time for ACPL-x6xL
at 3.3V and 5V.
VDD2 =1V (typ)
High
Impedence
VDD2
Output
High
Impedence
Rise Time (VDD = 5.0V)
30
25
20
15
10
5
10pF
15pF
22pF
33pF
47pF
100pF
0
-40 -20 0 20 40 60
Temperature (°C)
Fall Time (VDD = 5.0V)
25
20
15
10
5
10pF
15pF
22pF
33pF
47pF
100pF
0
-40 -20 0 20 40 60
Temperature (°C)
Rise Time (VDD = 3.3V)
25
20
15
80 100
80 100
500µs i. LED is off
Figure 13. VDD Ramp when LED is off.
VDD2 =2V (typ)
VDD2
VDD2 =1V (typ)
10
5
10pF
15pF
22pF
33pF
47pF
100pF
0
-40 -20 0 20 40 60 80 100
Temperature (°C)
Fall Time (VDD = 3.3V)
25
20
High
Impedence
Output
High
Impedence
500µs
ii. LED is on
discharge delay,
depending on the power
supply slew rate
Figure 14. VDD Ramp when LED is on.
15
10
5
10pF
15pF
22pF
33pF
47pF
100pF
0
-40 -20 0 20 40 60 80 100
Temperature (°C)
Figure 15. Rise and Fall time of ACPL-x6xL across wide load capacitance
15
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