ACPL-W70L-500E 데이터 시트보기 (PDF) - Avago Technologies

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ACPL-W70L-500E

Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature

Avago Technologies 

VDD2

VO

5pF

GND2

½ R total

ILP

½ R total

C LA

Table 1. Effects of Common Mode Pulse Direction on Transient ILED

If

dVCM/dt Is:

then

ILP Flows:

and

ILN Flows:

ILN CLC

SHIELD

If |ILP| < |ILN|,

LED IF Current

Is Momentarily:

positive (>0) away from LED anode through CLA away from LED cathode through CLC increased

negative (<0) toward LED anode through CLA

toward LED cathode through CLC

decreased

VDD2

0.1µF

VO

15pF

If |ILP| < |ILN|,

LED IF CurrenGtND2

Is Momentarily:

decreased

increased

74L504

(ANY

TTL/CMOS

GATE

VDD

CMR with Other Drive Circuits

CMR performance with drive circuits other than that

show½nR tiontalFigure 13 may be enhanced by followingVtDhD2ese

guidelines:

ILP

1.

UL½EsDeR toointfaldthrieveLEcDirc“uoiftfsC”wLsAthaetere(acsursrheonwt ins

shunted froVmO the

0in.1µFFigures 15 and

16). This is beneficial for good CMH.

15pF

2. UresceommofendtSyaHptILiIiNoEcLnaDC.lLC IFH

=

6mA

per

datasheet

GND2

Using any one of the drive circuits in Figures 15-17 with

IF = 6 mA will result in a typical CMR of 10 kV/μs for ACPL-

W70L AND ACPL-K73L, as long as the PC board layout

practices are followed. Figure 15 shows a circuit which can

be used with any totem-pole-output TTL/LSTTL/HCMOS

logic gate. The buffer PNP transistor allows the circuit to

be used with logic devices which have low current-sinking

capability. It also helps maintain the driving-gate power-

ssuhpifVtpDiDnlygcfuorrreontht eartdaevciocensstcaonntnleecvteeldtotomthineiminAiCpzPeuL-tW-gs7ru0opLupnldy

ground.

530 Ω

VDD

74L504

(ANY

TTL/CMOS

G7A4THE)C00

(OR ANY

OPEN-COLLECTOR

/OPEN-DRAIN

LOGIC GATE)

ACPL-W70L

530 Ω

ACPL-W70L

530 Ω

2N3906

1

(ANY PNP)

1

3

3

LED

LED

Figure 16. TTL open-collector/open drain gate drive circuit for ACPL-W70L

families.

VDD

ACPL-W70L

VD

74HC0

(OR AN

TOTEM-POL

OUTPUT LOGI

GATE

VDD

1

1

530 Ω

74HC00

(OR ANY

OPEN-COLLECTOR

/OPEN-DRAIN

LOGIC GATE)

74L504

(ANY

530 Ω

2N3906

(ANY PNP)

ACPL-W70L LED

3

1

LED

74HC04

(OR ANY

TOTEM-POLE

OUTPUT LOGIC

GATE)

LED

3

TTL/CMOS

GATE)

3

Figure 17. CMOS gate drive circuit for ACPL-W70L families.

Figure 15. TTL interface circuit for the ACPl-W70L families.

When using an open-collector TTL or open-drain CMOS

logic gate, the circuit in Figure 16 may be used. When

using a CMOS gate to drive the optocoupler, the circuit

shown in Figure 17, where the resistor is recommended to

connect to the anode of the LED, may be used.

-W70L

VDD

13

530 Ω

ACPL-W70L

1

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