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ACS8530 Datasheet PDF : 152 Pages
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ACS8530 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Fast External Switching Mode-SCRSW Pin
Fast external switching mode, for fast switching between
inputs I3 or I5 and I4 or I6, can also be triggered directly
from a dedicated pin SRCSW (Figure 4), once the mode
has been initialized.
The mode is initialized by either holding SRCSW pin High
Output Clock Phase Continuity on Source
Switchover
If either PBO is selected on (default), or, if DPLL frequency
limit is set to less than ±30 ppm or (±9.2 ppm default), the
device will always comply with GR-1244-CORE[19]
specification for Stratum 3 (maximum rate of phase
change of 81 ns/1.326 ms), for all input frequencies.
during reset (SRCSW must remain High for at least a
further 251 ms after PORB has gone High - see following
Modes of Operation
Note), or by writing to Reg. 48 Bit 4. After External
The ACS8530 has three primary modes of operation
Protection Switching mode has been initialized, the value
on this pin directly selects either I3/I5 (SRCSW High) or
I4/I6 (SRCSW Low). If this mode is initialized at reset by
pulling the SRCSW pin High, then it configures the default
(Free-run, Locked and Holdover) supported by three
secondary, temporary modes (Pre-Locked, Lost-Phase
and Pre-Locked2). These are shown in the State
Transition Diagram for the T0 DPLL, Figure 5.
frequency tolerance of I3/I5 and I4/I6 to ±80 ppm
(Reg. 41 and Reg. 42) as opposed to the normal
frequency tolerance of ±9.2 ppm. Any of these registers
can be subsequently set by external software, if required.
The ACS8530 can operate in Forced or Automatic control.
On reset, the ACS8530 reverts to Automatic Control,
where transitions between states are controlled
completely automatically. Forced Control can be invoked
by configuration, allowing transitions to be performed
Note...The 251 ms comprises 250 ms allowance for the
internal reset to be removed plus 1 ms allowance for APLLs to
start-up and become stable.
Selection of either input I3 or I5 is determined by the
under external control. This is not the normal mode of
operation, but is provided for special occasions such as
testing, or where a high degree of hands-on control is
required.
Priority value of I3; if the programmed priority of I3 is 0, Free-run Mode
then I5 is selected. Similarly, I6 is selected if the
programmed priority of I4 is 0.
Figure 4 I3/I5 and I4/I6 Switching
I3 Priority >0
I3
1
SRCSW
1
I5
0
I4
1
0
I6
0
T0 DPLL
I4 Priority >0
F8530D_006IPSWI3I4I5I6_01
When external protection switching is enabled, the device
The Free-run mode is typically used following a power-on
reset or a device reset before network synchronization
has been achieved. In the Free-run mode, the timing and
synchronization signals generated from the ACS8530 are
based on the 12.800 MHz clock frequency provided from
the external oscillator and are not synchronized to an
input reference source. By default, the frequency of the
output clock is a fixed multiple of the frequency of the
external oscillator, and the accuracy of the output clock is
equal to the accuracy of the oscillator. However the
external oscillator frequency can be calibrated to improve
its accuracy by a software calibration routine using
register cnfg_nominal_frequency (Reg. 3C and 3D). For
example a 500 ppm offset crystal could be made to look
like one accurate to within ±0.02 ppm.
The transition from Free-run to Pre-locked occurs when
the ACS8530 selects a reference source.
will operate as a simple switch. All clock monitoring is
disabled and the DPLL will simply be forced to try to lock Pre-locked Mode
on to the indicated reference source. Consequently the
device will always indicate “locked” state in the
sts_operating register (Reg. 09, Bits 2:0).
The ACS8530 will spend a maximum of 100 seconds in
the Pre-locked mode. If the device is required to spend up
to 700 seconds acquiring lock (e.g. in a Stratum3E
Revision 3.02/November 2005 © Semtech Corp.
Page 16
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