AD5245(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD5245 Datasheet PDF : 16 Pages
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POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 44), it is important to power
VDD/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
AD5245
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 45). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
VDD
C3 + C1
10µF 0.1µF
VDD
AD5245
GND
Figure 45. Power Supply Bypassing
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
W1
8A
VDD 2 AD5245 7 B
GND 3 TOP VIEW 6 AD0
SCL 4 (Not to Scale) 5 SDA
Figure 46.
PIN FUNCTION DESCRIPTIONS
Table 9.
Pin Name Description
1W
W Terminal.
2
VDD
Positive Power Supply.
3 GND Digital Ground.
4 SCL Serial Clock Input. Positive edge triggered.
5 SDA Serial Data Input/Output.
6 AD0 Programmable address bit 0 for multiple
package decoding.
7B
B Terminal.
8A
A Terminal.
Rev. 0 | Page 15 of 16
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