5962-9089401MEA 데이터 시트보기 (PDF) - Analog Devices
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5962-9089401MEA Datasheet PDF : 14 Pages
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AD526
HIGH ACCURACY A/D CONVERTERS
Very high accuracy and high resolution floating-point A/D con-
verters can be achieved by the incorporation of offset and gain
calibration routines. There are two techniques commonly used
for calibration, a hardware circuit as shown in Figure 43 and/or
a software routine. In this application the microprocessor is
functioning as the autoranging circuit, requiring software over-
head; therefore, a hardware calibration technique was applied
which reduces the software burden. The software is used to set
the gain of the AD526. In operation the signal is converted, and
if the MSB of the AD574 is not equal to a Logical 1, the gain is
increased by binary steps, up to the maximum gain. This maxi-
mizes the full-scale range of the conversion process and insures
a wide dynamic range.
The calibration technique uses two point correction, offset and
gain. The hardware is simplified by the use of programmable
magnitude comparators, the 74ALS528s, which can be “burned”
for a particular code. In order to prevent under or over range
hunting during the calibration process, the reference offset and
gain codes should be different from the endpoint codes. A cali-
bration cycle consists of selecting whether gain or offset is to be
calibrated then selecting the appropriate multiplexer channel to
apply the reference voltage to the signal channel. Once the op-
eration has been initiated, the counter, a 74ALS869, drives the
D/A converter in a linear fashion providing a small correction
voltage to either the gain or offset trim point of the AD574. The
output of the A/D converter is then compared to the value pre-
set in the 74ALS528 to determine a match. Once a match is
detected, the 74ALS528 produces a low going pulse which stops
the counter. The code at the D/A converter is latched until the
next calibration cycle. Calibration cycles are under the control
of the microprocessor in this application and should be imple-
mented only during periods of converter inactivity.
NOISE
REDUCTION
1F
–15V +15V
R8
A1
AD588
R1 R4
R2 R5
R3 A2
R6
A3
A4
+VS
–VS
+5V
0.1F
0.1F
VIN1
–5V VIN2
+15V
SYS
GND
VIN3
VIN4
–15V WR
AD7501 10k⍀
F
S
AD526
DECODED WR
ADDRESS
DECODED
ADDRESS
200pF
AD585
–15V +15V
VREF
WR
DE-
CODED
ADD
+5V
+
10F
+15V –15V
10F
+
7404
2
1
+15V
MSB
AD574
OP27
–15V
1k⍀
50k⍀
LSB
+5V
DATA
BUS
+5V
MSB
74ALS
528
P=Q
GAIN
LSB
MSB
74ALS
528
P=Q
OFFSET
LSB
ADDRESS BUS
12
12
PIN 28
AD574
7475
+5V
7475
1/2
7475
1/2
+5V
CALIBRATION
PRESET +5V
VALUE
+5V
5k⍀
1
3
2 7400
4
6
5 7400
ADG221
WR
MSB
74ALS
869
LSB
NOTE: ALL BYPASS CAPACITORS ARE 0.1F
VREF
AD7628
RFB A
INPUT
BUFFER
LATCH DAC A
PIN 15
AD588 R62
20k⍀
R5
20k⍀
R72
A2
R21
C12
10k⍀ R11
5k⍀
GAIN
AD712
OUT A
A1
AGND
AD712
CONTROL
LOGIC
WR
A/B
RFB B
LATCH DAC B
VREF
R41
C22
OUT B A3
AD712 R92
AGND
10k⍀
PIN 15
AD588
R102
20k⍀
R12
5k⍀
R8
20k⍀
A2
OFFSET
AD712
AGND
+5V
Figure 43. High Accuracy A/D Converter
REV. D
–13–
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