AD5543(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD5543 Datasheet PDF : 12 Pages
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AD5543/AD5553
APPLICATIONS
Stability
VDD
U1
VDD
RFB
C1
VREF
VREF
GND
IOUT
VO
AD8628
AD5543/AD5553 U2
Figure 7. Optional Compensation Capacitor for Gain
Peaking Prevention
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout technique must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node.
An optional compensation capacitor C1 can be added for stability
as shown in Figure 7. C1 should be found empirically but 20 pF
is generally adequate for the compensation.
Positive Voltage Output
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resistor’s
tolerance errors. To generate a negative reference, the reference
can be level-shifted by an op amp such that the VOUT and GND
pins of the reference become the virtual ground and –2.5 V
respectively, (see Figure 8).
+5V
ADR03
VOUT VIN
U4 +5V
U1
V+
1/2AD8620
V–
GND
U3
–2.5V
VDD
VREF
RFB
C1
IOUT
VO
GND
1/2AD8628
–5V
AD5543/AD5553
U2 0 < VO < +2.5
Figure 8. Positive Voltage Output Configuration
Bipolar Output
The AD5543/AD5553 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier
U4 configured as a summing amplifier (see Figure 9). In this
circuit, the second amplifier U4 provides a gain of 2 that increases
the output span magnitude to 5 V. Biasing the external amplifier
with a 2.5 V offset from the reference voltage results in a full
4-quadrant multiplying circuit. The transfer equation of this circuit
shows that both negative and positive output voltages are created
as the input data (D) is incremented from code zero (VOUT =
–2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V).
VOUT = (D / 32,768 – 1) × VREF (AD5543)
(3)
VOUT = (D /16,384 – 1) × VREF (AD5553)
(4)
For AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.
R1 R2
10k⍀؎0.01% 10k⍀؎0.01%
C2
+5V
ADR03 U1
VDD RFB
C1
+5V VOUT VIN
VREF
IOUT
GND
U3
GND
U4 +5V
5k⍀؎0.01%
R3
V+
VO
1/2AD8620
V–
1/2AD8620
–5V
–2.5 < VO < +2.5
AD5553 ONLY U2
Figure 9. Four-Quadrant Multiplying Application Circuit
–8–
REV. A
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