AD5545(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD5545 Datasheet PDF : 16 Pages
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SDI
CLK
CS
LDAC
A1
A0 D15 D14 D13 D12 D11 D10
tCSS
tDS
tDH
tCH
tCL
Figure 3. AD5545 18-Bit Data Word Timing Diagram
AD5545/AD5555
D1
D0
INPUT REG LD
tCSH
tLDS
tLDH
tLDAC
02918-0-003
SDI
A1
A0 D13 D12 D11 D10 D09 D08
D1
D0
CLK
INPUT REG LD
CS
tCSS
tDS
tDH
tCH
tCL
tCSH
LDAC
Figure 4. AD5555 16-Bit Data Word Timing Diagram
tLDS
tLDH
tLDAC
02918-0-004
Table 4. AD5545 Control Logic Truth Table
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No Effect
LL
H
HX
No Effect
L ↑+ H
HX
Shift Register Data
Advanced One Bit
LH
H
HX
No Effect
↑+ L
H
HX
No Effect
HX
L
HX
H
HX
↑+
HX
H
HX
H
HX
HX
HX
L0
LH
No Effect
No Effect
No Effect
No Effect
No Effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC Updated
with Current SR Current
Latched
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x8000
NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x8000
Rev. 0 | Page 7 of 16
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