AD5545(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD5545 Datasheet PDF : 16 Pages
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AD5545/AD5555
Table 5. AD5555 Control Logic Truth Table
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No Effect
LL
H
HX
No Effect
L ↑+ H
HX
Shift Register Data
Advanced One Bit
LH
H
HX
No Effect
↑+ L
H
HX
No Effect
HX
L
HX
H
HX
↑+
HX
H
HX
H
HX
HX
HX
L0
LH
No Effect
No Effect
No Effect
No Effect
No Effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC Updated
with Current SR Current
Latched
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x2000
NOTES
1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x2000
Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only
the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word
A1
A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only
the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 8. Address Decode
A1 A0 DAC Decoded
0 0 None
0 1 DAC A
1 0 DAC B
1 1 DAC A and DAC B
Rev. 0 | Page 8 of 16
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