AD5545(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD5545
(Rev.:Rev0)

Dual, Current-Output, Serial-Input, 16-/14-Bit DAC

Analog Devices 

AD5545/AD5555

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

RFBA 1

VREFA 2

IOUTA 3

AGNDA 4

AGNDB 5

IOUTB 6

VREFB 7

RFBB 8

AD5545/

AD5555

TOP VIEW

(Not to Scale)

16 CLK

15 LDAC

14 MSB

13 VDD

12 DGND

11 CS

10 RS

9 SDI

02918-0-002

Figure 2. 16-Lead TSSOP

Table 3. Pin Function Descriptions—16-Lead TSSOP

Pin No.

Mnemonic

Function

1

RFBA

Establish voltage output for DAC A by connecting to external amplifier output.

2

VREFA

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage.

Pin can be tied to VDD pin.

3

IOUTA

DAC A Current Output.

4

AGNDA

DAC A Analog Ground.

5

AGNDB

DAC B Analog Ground.

6

IOUTB

DAC B Current Output.

7

VREFB

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.

Pin can be tied to VDD pin.

8

RFBB

Establish voltage output for DAC B by connecting to external amplifier output.

9

SDI

Serial Data Input. Input data loads directly into the shift register.

10

RS

RESET Pin, Active Low Input. Input registers and DAC registers are set to all 0s or

midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and

0x2000 for AD5555 when MSB = 1.

11

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial

register data to the input register when CS/LDAC returns high. This does not affect LDAC

operation.

12

DGND

Digital Ground Pin.

13

VDD

Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%.

14

MSB

MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-

on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can

also be tied permanently to ground or VDD.

15

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to

DAC registers. Asynchronous active low input. See Table 4 and Table 5 for operation.

16

CLK

Clock Input. Positive edge clocks data into shift register.

Rev. 0 | Page 6 of 16

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