AD6655
SWITCHING SPECIFICATIONS—AD6655BCPZ-80/AD6655BCPZ-105
Table 7.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCLKH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3 Through Divide-by-8 Modes, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Noninterleaved Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Noninterleaved Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Interleaved and IQ Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Interleaved and IQ Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled
Pipeline Delay (Latency) NCO Enabled, FIR and fS/8 Mix Disabled
(Complex Output Mode)
Pipeline Delay (Latency) NCO, FIR, and fS/8 Mix Enabled
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
AD6655BCPZ-80
Temp Min Typ Max
Full
625
Full 20
80
Full 10
80
Full
12.5
Full 3.75 6.25 8.75
Full 5.63 6.25 6.88
Full
1.6
Full
0.8
Full
1.6 3.9 6.2
Full
4.0 5.4 7.3
Full
14.0
Full
11.0
Full
1.9 4.1 6.4
Full
4.4 5.8 7.7
Full
14.2
Full
10.8
Full
1.6 3.9 6.2
Full
3.4 4.8 6.7
Full
7.15
Full
5.35
Full
1.9 4.1 6.4
Full
3.8 5.2 7.1
Full
7.35
Full
5.15
Full
2.5 4.8 7.0
Full
3.7 5.3 7.3
Full
38
Full
38
Full
109
Full
1.0
Full
0.1
Full
350
Full
2
1 Conversion rate is the clock rate after the divider.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors.
AD6655BCPZ-105
Min Typ Max
625
20
105
10
105
9.5
2.85 4.75 6.65
4.28 4.75 5.23
1.6
0.8
1.6 3.9 6.2
4.0 5.4 7.3
11.0
8.0
1.9 4.1 6.4
4.4 5.8 7.7
11.2
7.8
1.6 3.9 6.2
3.4 4.8 6.7
5.65
3.85
1.9 4.1 6.4
3.8 5.2 7.1
5.85
3.65
2.5 4.8 7.0
3.7 5.3 7.3
38
38
109
1.0
0.1
350
2
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
Cycles
ns
ps rms
us
Cycles
Rev. 0 | Page 13 of 84