AD6655 데이터 시트보기 (PDF) - Analog Devices

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AD6655

IF Diversity Receiver

Analog Devices 

AD6655

CLK+

DECIMATED

INTERLEAVED

CMOS DATA

DECIMATED

INTERLEAVED

FD DATA

DECIMATED

DCO

tPD

CHANNEL A:

DATA

CHANNEL B:

DATA

CHANNEL A:

DATA

CHANNEL B:

DATA

tDCO

CHANNEL A:

DATA

CHANNEL B:

DATA

CHANNEL A:

FD BITS

CHANNEL B:

FD BITS

CHANNEL A:

FD BITS

tS

tH

CHANNEL B:

FD BITS

CHANNEL A:

FD BITS

CHANNEL B:

FD BITS

Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing

CLK+

DECIMATED

CMOS IQ

OUTPUT DATA

CMOS FD

DATA

DECIMATED

DCOA/DCOB

tPD

CHANNEL A/B:

Q DATA

CHANNEL A/B:

I DATA

CHANNEL A/B:

Q DATA

tDCO

CHANNEL A/B:

I DATA

CHANNEL A/B:

Q DATA

CHANNEL A/B:

I DATA

CHANNEL A/B:

FD BITS

CHANNEL A/B:

FD BITS

tS

tH

CHANNEL A/B:

FD BITS

CHANNEL A/B:

FD BITS

CHANNEL A/B:

FD BITS

Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing

CHANNEL A/B:

FD BITS

CLK–

CLK+

LVDS

DATA

LVDS

FAST DET

DCO–

DCO+

tPD

CHANNEL A:

DATA

CHANNEL A:

FD

CHANNEL B:

DATA

CHANNEL B:

FD

CHANNEL A:

DATA

CHANNEL A:

FD

tDCO

CHANNEL B:

DATA

CHANNEL B:

FD

CHANNEL A:

DATA

CHANNEL A:

FD

Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing

CLK+

SYNC

tSSYNC

tHSYNC

Figure 7. SYNC Timing Inputs

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