AD7570 데이터 시트보기 (PDF) - Analog Devices

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AD7570

CMOS 10-Bit Monolithic A/D Converter

Analog Devices 

FUNCTIONAL ANALYSIS

BASIC DESCRIPTION

(STRT) goes HIGH, the MSB(DB9) is set to the Logic "1"

The AD7570 is a monolithic CMOS AID converter which uses

the successive approximations technique to provide up to 10

state, while DBO through DB8 are reset to the "0" state.

Two clock pulses plus 200ns after STRT retUrns LOW, the

t

bits of digital data in a serial and parallel format. Most AID

MSB decision is made, and DB8 is tried. Each succeeding trial

applications require the addition of only a comparator and a

voltage or current reference.

and decision is made at tCLK + 200ns.

In the successive approximations technique, successive bits,

starting with the most significant bit (DB9) are applied to the

input of the 01 A converter. The DAC output is then com-

pared to the unknown analog input voltage (AIN) using a zero

crossing detector (comparator). If the DAC output is greater

than AIN, the data latch for the trial bit is reset to zero, and

Serial NRZ data is available during conversion at the SRO

terminal. SYNC provides 10 positive edges which occur in the

middle of each serial output bit. SYNC out must be used in

conjunction with SRO to avoid misinterpretation of data.

Both SYNC and SRO "float" when conversion is not taking

place.

the next smaller data bit is tried. If the DAC output is less

than AIN, the trial data bit stays in the "1" state, and the next

8-BIT SHORT CYCLE NOTES

smaller data bit is tried.

If the AD7570 is short cycled to 8 bits (SC8 = OV), the

Each successive bit is tried, compared to AIN, and set or reset

in this manner until the least significant bit (DBO) decision is

made. At this time, the AD7570 output is a valid digital rep-

resentation of the analog input, and will remain in the data

latches until another convert start (STRT) is applied.

OTIMING DESCRIPTION

B Figure 6 is the AD7570 timing diagram, showing the successive

trials and decisions for each data bit. When convert start

following will occur:

1. The SYNC terminal will provide 8, instead of 10, positive

output pulses.

2. OBI goes "high" coincident with the LSB (DB2 is the LSB

when short cycled to 8 bits) decision, and remains high

until another STRT is initiated. DBO remains in the "0"

state.

3. BUSY goes "high" one clock period after the DB2 (DB2 is

the LSB when short cycled) decision is made.

SO ClK1

II L STRT2

E SYNC3, 4,8

TE SROS,8

---------

,

IMSBI8 17 f6l 5 14 13 1211 !LSBr---------

t

t

OB9 (MSB)6,7 :///////1 TRYMSB1-- MSBDECISION

0B87 ////////1T RY'DBB-! E DB8DECISION

OB77 ////////1

TRYDB7--/ I~ DB7 DECISION

OB67 ////////1

OB57 ///////~

TRY DB6==:/ E DB6 DECISION

~ TRY DB5

E DBS DECISION

t

0B47 ////////1

d TRY DB4

E DB4 DECISION

OB37 :///////~

OB27 ////////1

~ TRY DB3

E DB3 DECISION

TRY DB2==:1 EDB2 DECISION

OB17 ////////1

TRY DB1 ==:/ E DB1 DECISION

DBa (lSB)7 all////~

TRY LSB ==:/

E DBO (LSBI DECISION

BSEN2

BUSY

--

, BUSY JCONVERT L.-. - - -

COMPLETE

NOTES:

1. INTERNAL CLOCK RUNS ONLY DURING CONVERSION CYCLE (EXTERNAL CLOCK SHOWN!.

2. EXTERNALLY INITIATED.

3. SERIAL SYNC LAGS CLOCK BY '" 200ns.

4. DOTTED LINES INDICATE "FLOATING" STATE.

5. FOR ILLUSTRATIVEPURPOSES,SERIAL OUTSHOWNAS 1101001110.

6. CROSS HATCHING INDICATES "DON'T CARE" STATE.

7. SET AND RESET OF OUTPUT DATA BITS LAGS CLOCK POSITIVE EDGE BY '" 200ns.

8. SHOWN FOR sca = 1.

411

Figure 6. AD7570 Conversion Timing Sequence

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