AD7849 데이터 시트보기 (PDF) - Analog Devices
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AD7849 Datasheet PDF : 20 Pages
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AD7849
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are no subject to test. VREF+ = 5 V; VDD = 14.25 V to 15.75 V; VSS = −14.25 V to
−15.75 V; VCC = 4.75 V to 5.25 V; ROFS connected to 0 V.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Settling Time1
Slew Rate
Digital-to-Analog Glitch Impulse
AC Feedthrough
Digital Feedthrough
Output Noise Voltage Density, 1 kHz to 100 kHz
A, B, C Versions
7
10
4
250
150
1
5
80
Unit
μs typ
μs typ
V/μs typ
nV-sec typ
nV-sec typ
mV p-p typ
nV-sec typ
nV/√Hz typ
Test Conditions/Comments
To 0.006% FSR. VOUT loaded. VREF− = 0 V.
To 0.003% FSR. VOUT loaded. VREF− = −5 V.
DAC alternatively loaded with 00 … 00 and
111 … 11. VOUT loaded. LDAC permanently low.
BIN/COMP set to 1. VREF− = −5 V.
LDAC frequency = 100 kHz.
VREF− = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s. BIN/COMP set to 0.
DAC alternatively loaded with all 1s and 0s.
SYNC high.
Measured at VOUT. VREF+ = VREF− = 0 V.
BIN/COMP set to 0.
1 LDAC = 0. Settling time does not include deglitching time of 5 μs (typical).
TIMING CHARACTERISTICS
VDD = 14.25 V to 15.75 V; VSS = −14.25 V to −15.75 V; VCC = 4.75 V to 5.25 V; RL = 2 kΩ, CL = 200 pF. All specifications TMIN to TMAX,
unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a
voltage level of 1.6 V.
Table 4.
Parameter
t1 1
t2
t3
t4
t5
t6 2
t7
tr
tf
Limit at 25°C (All Versions)
200
50
70
10
40
80
80
30
30
Limit at TMIN, TMAX (All Versions)
200
50
70
10
40
80
80
30
30
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
μs max
μs max
Test Conditions/Comments
SCLK cycle time
SYNC-to-SCLK setup time
SYNC-to-SCLK hold time
Data setup time
Data hold time
SCLK falling edge to SDO valid
LDAC, CLR pulse width
Digital input rise time
Digital input fall time
1 SCLK mark/space ratio range is 40/60 to 60/40.
2 SDO load capacitance is 50 pF.
Rev. C | Page 5 of 20
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